Patents by Inventor Richard C. Murphy

Richard C. Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hierarchical memory systems
    Patent number: 11036434
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
  • STORAGE DEVICE OPERATION ORCHESTRATION
    Publication number: 20210157491
    Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.
    Type: Application
    Filed: February 5, 2021
    Publication date: May 27, 2021
    Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
  • MEMORY ACCESS DETERMINATION
    Publication number: 20210157749
    Abstract: Apparatuses and methods related to computer memory access determination are described. A command can be received at a memory system (e.g., a system with or exploiting DRAM). The command can comprise a memory operation and a plurality of privilege bits. The privilege level or a memory address that is associated with the memory operation can be identified. The privilege level can correspond to the memory address can describe a privilege level that can access the memory address. A determination can be made as to whether the memory operation, or the application requesting certain data or prompting corresponding instructions, is entitled to access to the memory address using the plurality of privilege bits and the privilege level. Responsive to determining that the memory operation has access to the memory address, the memory operation can be processed.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventor: Richard C. Murphy
  • Apparatuses and methods for compute in data path
    Patent number: 11011220
    Abstract: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES
    Publication number: 20210142845
    Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 13, 2021
    Inventor: Richard C. Murphy
  • Multiple memory type memory module systems and methods
    Patent number: 11003596
    Abstract: The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Hierarchical memory systems
    Patent number: 10996975
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
  • IN-MEMORY LIGHTWEIGHT MEMORY COHERENCE PROTOCOL
    Publication number: 20210125649
    Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 29, 2021
    Inventor: Richard C Murphy
  • APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS
    Publication number: 20210118486
    Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Perry V. Lea, Richard C. Murphy
  • Extended memory operations
    Patent number: 10983795
    Abstract: Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
  • Apparatuses and methods for compute enabled cache
    Patent number: 10970218
    Abstract: The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • TRANSLATION LOOKASIDE BUFFER IN MEMORY
    Publication number: 20210096748
    Abstract: Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Inventors: John D. Leidel, Richard C. Murphy
  • Apparatuses and methods for scatter and gather
    Patent number: 10964358
    Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Kelley D. Dobelstein, Timothy P. Finkbeiner, Richard C. Murphy
  • Storage device operation orchestration
    Patent number: 10949101
    Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
  • SPIKING NEURAL UNIT
    Publication number: 20210064963
    Abstract: Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
  • APPARATUSES AND METHODS FOR PERFORMING BACKGROUND OPERATIONS IN MEMORY USING SENSING CIRCUITRY
    Publication number: 20210065765
    Abstract: Apparatuses and methods can be related to performing operations in memory. Operations can be performed in the background while the memory is performing different operations. For example, comparison operations can be performed by the memory device while the memory device is reading data. The results of the comparison operations can be stored in registers of the memory device. The registers can be made accessible externally to the memory device.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
  • ROW ACTIVATION PREVENTION USING FUSES
    Publication number: 20210064743
    Abstract: Apparatuses and methods can be related to preventing the activation of rows using fuses in, for example, a memory device or a computing system that includes a memory device. The preventing the activation of rows adjacent to a predefined row address range can reduce the charge leakage from the memory cells comprising the predefined row address range. Reducing the charge leakage from memory cells comprising the predefined row address range can increase stability in data retention.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
  • ROW HAMMER MITIGATION
    Publication number: 20210065775
    Abstract: Apparatuses and methods related to row hammer mitigation in, for example, a memory device or a computing system that includes a memory device. Data from a group of memory cells of a memory array can be latched in sensing circuitry responsive to a determination of a hammering event associated with the group of memory cells. Thereafter, the data can be accessed from the sensing circuitry.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
  • COMPARISON OPERATIONS IN MEMORY
    Publication number: 20210065778
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • HIERARCHICAL MEMORY SYSTEMS
    Publication number: 20210056037
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving a request to access data via an input/output (I/O) device, determining whether the data is stored in a non-persistent memory device or a persistent memory device, and redirecting the request to access the data to logic circuitry in response to determining that the data is stored in the persistent memory device.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy