Abstract: At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

Abstract: A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: A programmable logic array integrated circuit is provided which comprises: a plurality of logic array blocks in which respective logic array blocks include, multiple respective programmable logic elements and respective random access memory arrays and corresponding memory access control circuitry and respective shared programmable local interfaces; and a network of conductors which is programmable to connect a respective local interface circuit of substantially any logic array block to a respective local interface of substantially any other logic array block.

Abstract: Disclosed is a current booster or kicker for an output amplifier of a programmable logic control or other integrated circuit. The current booster includes a control mechanism and an auxiliary voltage supply. When a change in output state is initiated, the control mechanism connects the auxiliary voltage supply to the output of the output amplifier. After a change in output state in completed, the control mechanism disconnects the auxiliary voltage supply from the output of the output amplifier. In this way, the output amplifier can drive a relatively high capacitance load at a relatively high slew rate.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: In an integrated circuit having circuit components such as SRAM cells requiring a finite voltage level for operation, a power on reset circuit includes one of the circuit components in its output so that a power on reset (POR) signal is generated upon power supply turn on and the POR signal is deasserted only after the circuit component becomes operational and responsive to a PORsignal generated by the reset circuit.