Patents by Inventor Richard Conti
Richard Conti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6740539Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: GrantFiled: February 13, 2003Date of Patent: May 25, 2004Assignees: International Business Machines Corporation, Infineon Technologies A.G.Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Patent number: 6667504Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.Type: GrantFiled: March 24, 2003Date of Patent: December 23, 2003Assignees: International Business Machines Corporation, Infineon Technologies North America CorporationInventors: Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr, Rolf Weis
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Publication number: 20030153198Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: ApplicationFiled: February 13, 2003Publication date: August 14, 2003Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Patent number: 6570256Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: GrantFiled: July 20, 2001Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Patent number: 6548357Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.Type: GrantFiled: April 8, 2002Date of Patent: April 15, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
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Publication number: 20030068853Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.Type: ApplicationFiled: November 18, 2002Publication date: April 10, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard A. Conti, Daniel C. Edelstein, Gill Yong Lee
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Patent number: 6531412Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.Type: GrantFiled: August 10, 2001Date of Patent: March 11, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Richard A. Conti, Daniel C. Edelstein, Gill Yong Lee
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Publication number: 20030032306Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.Type: ApplicationFiled: August 10, 2001Publication date: February 13, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard A. Conti, Daniel C. Edelstein, Gill Yong Lee
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Publication number: 20030017642Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: ApplicationFiled: July 20, 2001Publication date: January 23, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Patent number: 6500772Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.Type: GrantFiled: January 8, 2001Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Richard A. Conti, Chester Dziobkowski, Thomas Ivers, Paul Jamison, Frank Liucci
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Patent number: 6486015Abstract: Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.Type: GrantFiled: April 25, 2000Date of Patent: November 26, 2002Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Nirmal Chaudhary, Richard A. Conti
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Publication number: 20020127883Abstract: A CVD process for the deposition of silicon oxide by reacting BTBAS with an ozone reactant gas comprising providing a semiconductor wafer substrate in a single wafer reactor, contacting said substrate with a gaseous mixture containing a bis-tertiary butyl aminosilane reactant and an ozone reactant at a pressure ranging from about 10 Torr to about 760 Torr, and, heating said mixture at a temperature ranging from about 400 to about 600° C., whereby said reactants are reacted to deposit said oxide as a film on said substrate.Type: ApplicationFiled: January 9, 2001Publication date: September 12, 2002Inventors: Richard A. Conti, Ashima B. Chakravarti, Kerem Kapkin, Joseph C. Sisson
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Publication number: 20020111025Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.Type: ApplicationFiled: April 8, 2002Publication date: August 15, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
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Patent number: 6429149Abstract: A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.Type: GrantFiled: February 23, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Richard A. Conti, Laertis Economikos, Byeongju Park
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Publication number: 20020090835Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.Type: ApplicationFiled: January 8, 2001Publication date: July 11, 2002Inventors: Ashima B. Chakravarti, Richard A. Conti, Chester Dziobkowski, Thomas Ivers, Paul Jamison, Frank Liucci
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Patent number: 6403423Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.Type: GrantFiled: November 15, 2000Date of Patent: June 11, 2002Assignee: International Business Machines CorporationInventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
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Patent number: 6335261Abstract: A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface of the substrate; deposition on the surface adjacent the feature causes formation of an overhang structure partially blocking the opening. The fill material is then reacted with a reactant to form a solid reaction product having a greater specific volume than the fill material. The overhang structure is thus converted into a reaction product structure blocking the opening. The reaction product (including the reaction product structure) is then desorbed, thereby exposing unreacted fill material at the bottom of the feature. The depositing and reacting steps may be repeated, with a final depositing step to fill the feature. Each sequence of depositing, reacting and desorbing reduces the aspect ratio of the feature.Type: GrantFiled: May 31, 2000Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: Wesley Natzle, Richard A. Conti, Laertis Economikos, Thomas Ivers, George D. Papasouliotis
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Patent number: 6274440Abstract: A structure and method for making a cavity fuse over a gate conductor stack.Type: GrantFiled: March 31, 1999Date of Patent: August 14, 2001Assignee: International Business Machines CorporationInventors: Kenneth C. Arndt, Axel C. Brintzinger, Richard A. Conti, Donna R. Cote, Chandrasekhar Narayan, Ravikumar Ramachandran, Thomas S. Rupp, Senthil K. Srinivasan
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Patent number: 6247356Abstract: A hardness tester having a frame and a rotatable turret movably supported on the frame is provided. A plurality of load cells are fixedly mountable on the turret, and a plurality of indenters are fixedly attachable to the load cells, respectively. A user interface selectively provides signals to a motor to move the turret into contact with a test specimen via one of the indenters to thereby apply a load on the test specimen. The indenters are fixed with respect to the turret and do not move in relation to the turret when the turret is brought down to bear on the test specimen. The load cells measure the load applied to the test specimen. A closed loop control system receives load measurement signals from the load cells and controls movement of the turret, preventing the motor from applying load in excess of a predetermined selectable load amount input by a user via the user interface. The invention preferably includes a plurality of indenter adapters, each attached to respective undersides of the load cells.Type: GrantFiled: March 30, 1999Date of Patent: June 19, 2001Assignee: Instron CorporationInventors: John J. Merck, Jr., Richard Conti, Joerg Meissner, Patrick Micozzi
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Patent number: 6232222Abstract: A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.Type: GrantFiled: September 14, 1999Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Michael Armacost, Richard A. Conti, Jeffrey P. Gambino, Jeremy K. Stephens