Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

Abstract: An electronic or electrical device or component thereof comprising a protective polymeric coating on a surface of the electronic or electrical device or component thereof, wherein the polymeric coating is obtainable by exposing the electronic or electrical device or component thereof to a plasma comprising one or more saturated monomer compounds for a sufficient period of time to allow the protective polymeric coating to form on a surface thereof; wherein the one or more saturated monomer compounds each have a melting point at standard pressure of less than 45?C and a boiling point at standard pressure of less than 500° C.

Abstract: The present invention provides an electronic or electrical device or component thereof comprising a cross-linked polymeric coating on a surface of the electronic or electrical device or component thereof; wherein the cross-linked polymeric coating is obtainable by exposing the electronic or electrical device or component thereof to a plasma comprising a monomer compound and a crosslinking reagent for a period of time sufficient to allow formation of the cross-linked polymeric coating on a surface thereof, wherein the monomer compound has the following formula: where R1, R2 and R4 are each independently selected from hydrogen, optionally substituted branched or straight chain C1-C6 alkyl or halo alkyl or aryl optionally substituted by halo, and R3 is selected from: where each X is independently selected from hydrogen, a halogen, optionally substituted branched or straight chain C1-C6 alkyl, halo alkyl or aryl optionally substituted by halo; and n1 is an integer from 1 to 27; and wherein the crosslinkin

Abstract: An electronic or electrical device or component thereof having a coating formed thereon by exposing said electronic or electrical device or component thereof to a plasma comprising one or more monomer compounds for a sufficient period of time to allow a protective polymeric coating to form on a surface thereof; wherein the protective polymeric coating forms a physical barrier over a surface of the electronic or electrical device or component thereof; wherein each monomer is a compound of formula I(a): or a compound of formula I(b) wherein each of R1 to R9 is independently selected from hydrogen or halogen or an optionally substituted C1-C6 branched or straight chain alkyl group; each X is independently selected from hydrogen or halogen; a is from 0-6; b is from 2 to 14; and c is 0 or 1; and wherein when each X is F or when at least one X is halogen, in particular F, the FTIR/ATR intensity ratio of CX3/C?O of the coating is less than (c+1)0.6e?0.

Abstract: Technologies for providing error correction for row direction and column direction in a cross point memory include a memory that includes media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is configured to read, from the memory media, a column of data. Additionally, the media access circuitry is configured to read, from the memory media, column error correction code (ECC) check data appended to the column of data and perform error correction on the column of data with the column ECC check data to produce error-corrected data.

Abstract: Technologies for adding computational ability to memory devices without changing media layers include a process for the manufacture of a memory device. The process includes obtaining a memory media capable of communicating with multiple different types of media access circuitries through a set of communication paths at predefined locations. The process also includes obtaining a media access circuitry capable of communicating with the memory media through the communication paths at the predefined locations and connecting the obtained memory media to the obtained media access circuitry to enable communication through the communication paths at the predefined locations.

Abstract: The present invention provides an electronic or electrical device or component thereof comprising a cross-linked polymeric coating on a surface of the electronic or electrical device or component thereof; wherein the cross-linked polymeric coating is obtainable by exposing the electronic or electrical device or component thereof to a plasma comprising a monomer compound and a crosslinking reagent for a period of time sufficient to allow formation of the cross-linked polymeric coating on a surface thereof, wherein the monomer compound has the following formula: where R1, R2 and R4 are each independently selected from hydrogen, optionally substituted branched or straight chain C1-C6 alkyl or halo alkyl or aryl optionally substituted by halo, and R3 is selected from: where each X is independently selected from hydrogen, a halogen, optionally substituted branched or straight chain C1-C6 alkyl, halo alkyl or aryl optionally substituted by halo; and n1 is an integer from 1 to 27; and wherein the crosslinki

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Abstract: Technologies for performing hyper-dimensional operations in memory includes a device with a memory media and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to receiving the query, a reference hyper-dimensional vector associated with the query. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array in the memory media to determine a number of matching bit values for each row relative to the reference hyper-dimensional vector, wherein each bit in a column of the stochastic associative array represents a bit value of a corresponding row, identify a closest matching row that has a highest number of matching bit values, and output data of the closest matching row.

Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.

Abstract: Technologies for performing a hyper-dimensional operation in a memory of the compute device include a memory and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to a receipt of the query, a key hyper-dimensional vector associated with the query, perform a hyper-dimensional operation to determine a reference hyper-dimensional vector associated with a value to the key. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array of a hyper-dimensional vector table in the memory, identify a closest matching row in the stochastic associative array relative to the reference hyper-dimensional vector, wherein the closest matching row indicates a closest matching value hyper-dimensional vector, and output a value associated with the closest matching value hyper-dimensional vector.

Abstract: Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.

Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.

Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The request includes a search key indicative of the subset of bit data, and the search key is formed on a same axis as the rows. The compute device identifies one or more candidate data sets in the matrix based on a search for matching bit data of the search key with bit data in one or more of the columns. The compute device outputs the identified candidate data sets.

Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) using error correction codes include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The compute device identifies, based on a search performed on the columns in the matrix, one or more candidate data sets. Each candidate data set corresponds to one of the rows in the matrix. The compute device performs an error correction operation on the identified one or more candidate data sets to determine whether the identified one or more candidate data sets is an exact match with the subset of the bit data.

Abstract: Technologies for efficiently accessing data columns and rows in a memory include a device with circuitry configured to receive a request to access memory in which each bit of a logical column of bits is located in a different physical row and a different physical column than any other bit in the logical column. The circuitry is additionally configured to access, in response to the request, the memory.

Abstract: Technologies for efficiently performing scatter-gather operations include a device with circuitry configured to associate, with a template identifier, a set of non-contiguous memory locations of a memory having a cross point architecture. The circuitry is additionally configured to access, in response to a request that identifies the non-contiguous memory locations by the template identifier, the memory locations.