Abstract: A bounds evaluation unit generates a bounds measurement pair corresponding to a character pattern pair determined from a handwritten word. Within the bounds measurement pair, a first bounds measurement corresponds to a first character pattern, and a second bounds measurement corresponds to a second character pattern. The first and second bounds measurements are each a bounding box that defines a left-most, a right-most, a top-most, and a bottom-most extent of the corresponding character pattern. The bounds measurement pair is compared against one or more bounds model pairs, where each bounds model pair corresponds to a hypothesized character identifier pair in which each individual hypothesized character identifier has been determined by a character recognition unit. Each bounds model pair indicates the expected size and position of a character pattern pair corresponding to the hypothesized character identifier pair.

Abstract: A statically operated dynamic CMOS logic gate that includes an FET logic network for performing a predefined logic function with respect to its logic inputs, an output node, a precharge transistor, and in some embodiments an evaluate transistor. During operation, the precharge transistor is first turned on by a clock signal during a precharge phase to precharge an output node of the dynamic logic gate to a first voltage state. During the precharge phase, the evaluate transistor is turned off by the clock signal. An evaluate phase typically follows the precharge phase, and during the evaluation phase, the evaluate transistor is turned on by the control signal to allow the logic network to perform the predefined logic function with respect to its inputs, and the logic network selectively charges or discharges the output node to a second voltage state via the evaluate transistor in accordance with the predefined logic function given to the logic inputs to the logic gate.

Abstract: A filter capable of having its damping and frequency parameters independently varied. The filter can be represented in either a digital or an analog computation network. The network comprises four multipliers for multiplying by a frequency term twice and a damping factor twice. In addition, the network comprises two unit delay blocks for temporarily storing previous signal input values for zeros or output values for poles. These stored values are used in computing subsequent outputs. The multipliers are configured with adders and subtractors to compute a next output value as a combination of a current input, a weight-2+2df+f.sup.2 -wd.sup.2 f.sup.2 times the most recent saved value and a weight 1-2df+wd.sup.2 f.sup.2 times the previous saved value. Moreover, unity gain at DC can be achieved.

Abstract: A system for reconstructing a signal waveform from a correlogram is based upon the recognition that the information in each channel of the correlogram is equivalent to the magnitude of the Fourier transform of a signal. By estimating a signal on the basis of its Short-Time Fourier Transform Magnitude, each channel of information from a cochlear model can be reconstructed. Once this information is retrieved, a signal waveform can be resynthesized through inversion of the cochlear model. The process for reconstructing the cochlear model data can be optimized with the use of techniques for improving the initial estimate of the signal from the magnitude of its Fourier Transform, and by employing information that is known apriori about the signal during the estimation process, such as the characteristics of sound signals.

Abstract: A statically operated dynamic CMOS logic gate that includes an FET logic network for performing a predefined logic function with respect to its logic inputs, an output node, a precharge transistor, and in some embodiments an evaluate transistor. During operation, the precharge transistor is first turned on by a clock signal during a precharge phase to precharge an output node of the dynamic logic gate to a first voltage state. During the precharge phase, the evaluate transistor is turned off by the clock signal. An evaluate phase typically follows the precharge phase, and during the evaluation phase, the evaluate transistor is turned on by the control signal to allow the logic network to perform the predefined logic function with respect to its inputs, and the logic network selectively charges or discharges the output node to a second voltage state via the evaluate transistor in accordance with the predefined logic function given to the logic inputs to the logic gate.

Abstract: A filter capable of having its damping and frequency parameters independently varied. The filter can be represented in either a digital or an analog computation network. The network comprises four multipliers for multiplying by a frequency term twice and a damping factor twice. In addition, the network comprises two unit delay blocks for temporarily storing previous signal input values for zeros or output values for poles. These stored values are used in computing subsequent outputs. The multipliers are configured with adders and subtractors to compute a next output value as a combination of a current input, a weight -2+2df+f.sup.2 --wd.sup.2 f.sup.2 times the most recent saved value and a weight 1-2df+wd.sup.2 f.sup.2 times the previous saved value. Moreover, unity gain at DC can be achieved.

Abstract: A first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The gates of the first and second MOS transistors are connected to sources of input voltage which are of a magnitude smaller than the threshold voltages of the two MOS transistors. The first MOS transistor located next to the load is kept in saturation. A related circuit includes a first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The first MOS transistor located next to the load is kept in saturation. The gates of the first and second MOS transistors are connected to the gates of third and fourth diode-connected MOS transistors of the same conductivity type as the first and second MOS transistors. The third MOS transistor is connected between a first input current node and a fixed voltage source. The fourth MOS transistor is connected between a second input current node and a fixed voltage source.

Abstract: An improved computer memory system based on a novel four transistor memory cell and an improved address decoder circuit is disclosed. The memory cell can be fabricated using currently available logic fabrication processes and requires a silicon area less than that required by prior art static memory cells. The improved decoder can be fabricated in significantly less silicon area than existing NOR gate decoder arrays and is faster than existing NOR gate decoder arrays.

Abstract: An electronically variable active analog delay line utilizes cascaded differential transconductance amplifiers with integrating capacitors and negative feedback from the output to the input of each noninverting amplifier. The delay of each section may be controlled through a conductor having distributed resistance connected at distributed points to the transconductance control terminal of the amplifiers with a controllable voltage gradient between the two ends of the conductor. Signals may be coupled in and added to a propagating signal using capacitors, or transconductance amplifiers which may also be of the differential transconductance type, particularly when coupling signals from a second delay line having substantially the same propagation velocity.

Abstract: A processing element may be used either separately or in an array of similar processing elements for performing concurrent data processing calculations. The processing element includes a multiported memory unit for storing data to be processed by any of a plurality of function units which are connected to the multiported memory unit. The multiported memory unit includes a number of data storage slots for storing data words to be processed and the results of said processing. Each function unit performs a calculation having as its inputs one or or more data words from the multiported memory unit. The result of this calculation is stored back in the multiported memory unit. The transfer of data to and from the function units is accomplished by use of the ports on said multiported memory unit. The data manipulated by the processing element is controlled by specifying a correspondence between data storage slots, memory input ports and memory output ports.

Abstract: Speech and like signals are analyzed based on a model of the function of the human hearing system. The model of the inner ear is expressed as signal processing operations which map acoustic signals into neural representations. Specifically, a high order transfer function is modeled as a cascade/parallel filterbank network of simple linear, time-invariant second-order filter sections. Signal transduction and compression are based on a half-wave rectification with a non-linearly coupled, variable time constant automatic gain control network. The result is a simple device which simulates the complex signal transfer function associated with the human ear. The invention lends itself to implementation in digital circuitry for real-time or near real-time processing of speech and other sounds.

Abstract: An imaging array provides a plurality of distinguishable bitmap images and comprises an array of sensor cells capable of sensing radiation. The cells are connected in a manner to form distinguishable bitmap images through a pattern of correspondence among the cells. Each bitmap image formed comprises a combination of one or more cells indicative of detecting an image pixel within a field of array cells that have been nonindicative of such detection. The pattern of correspondence may be one of inhibition of the operation of other cells in the array or one of indication of operation to other cells in the array. Various patterns of correspondence can be created among the cells creative of bitmap images. Bitmap images may consist of combinations of responsive cells within a field of nonresponsive cells in the array.

Abstract: A cursor control device or "optical mouse" for use with an interactive display oriented computer system to provide movement for a visible cursor from position to position on a display screen of such a system. The device includes an IC chip that contains an optical sensor array and circuitry to bring about detectable bitmaps based upon a plurality of sensor cells making up the array. The distinguishable bitmaps are employed as a means for comparison to provide an output indicative of the direction and amount of movement of the cursor control device relative to an optical contrasting input to the array, the output is employed as a means to move the visible cursor from position to position on a display screen.

Abstract: A data and clock recovery system is provided in the signal handling receiver (SHRx) stage of an integrated MOS circuit data communication controller to provide accurate sampling of an incoming data packet for recovery of the data and data clock, regardless of differences in the electrical and environmentally affected characteristics of the circuit elements comprising the integrated MOS/VLSI semiconductor chip.

Abstract: A self-calibrated clock and timing signal generator provides reliable and continuous arbitrary digital waveforms of preselectable edge resolution. The generator comprises a multistage means to produce a time delayed signal of preselectable edge resolution and having a plurality of outputs or taps between a plurality of series connected delay stages comprising the multistage means. The delay per stage is substantially identical so that the selection of any one of the outputs is representative of a predetermined amount of delay provided to an input signal to the multistage means. Calibrating means is integrally included to develop a control signal which is coupled to each of the stages of the multistage means to continuously maintain the predetermined amount of delay per stage. In the embodiment described, the calibrating means takes the form of an automatic frequency control (AFC) loop wherein the frequency of a voltage controlled oscillator (VCO) is regulated to be equal to that of a reference frequency.