Patents by Inventor Richard Fastow
Richard Fastow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127896Abstract: A storage device includes a storage array having multiple decks of NAND cells in a three dimensional (3D) stack. There can be any number of decks that have multiple wordlines in vertical stacks. The decks include a first deck and a second deck. Bias circuitry can apply different voltages to different decks of the storage array. The bias circuitry can apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.Type: ApplicationFiled: December 23, 2023Publication date: April 18, 2024Inventors: Chao ZHANG, Xin SUN, Richard FASTOW, Giuseppina PUZZILLI, Krishna K. PARAT
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Publication number: 20230230639Abstract: Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.Type: ApplicationFiled: March 28, 2023Publication date: July 20, 2023Inventors: Mattia CICHOCKI, Violante MOSCHIANO, Tommaso VALI, Guido Luciano RIZZO, Chang Wan HA, Richard FASTOW
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Publication number: 20230033086Abstract: A memory array including a varying width channel is disclosed. The array includes a plurality of WLs, which are above a layer, where the layer can be, for example, a Select Gate Source (SGS) of the memory array, or an isolation layer to isolate a first deck of the array from a second deck of the array. The channel extends through the plurality of word lines and at least partially through the layer. In an example, the channel comprises a first region and a second region. The first region of the channel has a first width that is at least 1 nm different from a second width of the second region of the channel. In an example, the first region extends through the plurality of word lines, and the second region extends through at least a part of the layer underneath the plurality of word lines. In one case, the first width is at least 1 nm less than a second width of the second region of the channel.Type: ApplicationFiled: February 7, 2020Publication date: February 2, 2023Inventors: Chen WANG, Dipanjan BASU, Richard FASTOW, Dimitri KIOUSSIS, Yi LI, Ebony Lynn MAYS, Dimitrios PAVLOPOULOS, Junyen TEWG
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Patent number: 11500446Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.Type: GrantFiled: September 28, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Richard Fastow, Shankar Natarajan, Chang Wan Ha, Chee Law, Khaled Hasnat, Chuan Lin, Shafqat Ahmed
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Publication number: 20220359441Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.Type: ApplicationFiled: May 7, 2021Publication date: November 10, 2022Inventors: Khaled HASNAT, Prashant MAJHI, Owen JUNGROTH, Richard FASTOW, Krishna K. PARAT
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Publication number: 20220293189Abstract: Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Inventors: Chao Zhang, Krishna Parat, Richard Fastow, Ricardo Basco, Xin Sun, Heonwook Kim, Zhan Liu
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Patent number: 11322508Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed.Type: GrantFiled: June 1, 2018Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Krishna Parat, Richard Fastow
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Publication number: 20210096634Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.Type: ApplicationFiled: September 28, 2019Publication date: April 1, 2021Inventors: Richard FASTOW, Shankar NATARAJAN, Chang Wan HA, Chee LAW, Khaled HASNAT, Chuan LIN, Shafqat AHMED
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Patent number: 10923450Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.Type: GrantFiled: June 11, 2019Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Richard Fastow, Khaled Hasnat, Prashant Majhi, Owen W. Jungroth, Krishna Parat
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Publication number: 20200395328Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Applicant: Intel CorporationInventors: Richard Fastow, Khaled Hasnat, Prashant Majhi, Owen W. Jungroth, Krishna Parat
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Patent number: 10847234Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.Type: GrantFiled: April 26, 2019Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Han Zhao, Richard Fastow, Krishna K. Parat, Arun Thathachary, Narayanan Ramanan
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Publication number: 20200342946Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Inventors: Han ZHAO, Richard FASTOW, Krishna K. PARAT, Arun THATHACHARY, Narayanan RAMANAN
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Patent number: 10651153Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.Type: GrantFiled: June 18, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Richard Fastow, Khaled Hasnat, Prashant Majhi, Owen Jungroth
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Patent number: 10325665Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.Type: GrantFiled: December 8, 2017Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Richard Fastow, Xin Sun, Uday Chandrasekhar, Krishna K. Parat, Camila Jaramillo, Purval S. Sule, Aliasgar S. Madraswala
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Publication number: 20190043836Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.Type: ApplicationFiled: June 18, 2018Publication date: February 7, 2019Inventors: Richard FASTOW, Khaled HASNAT, Prashant MAJHI, Owen JUNGROTH
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Publication number: 20190043875Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed.Type: ApplicationFiled: June 1, 2018Publication date: February 7, 2019Inventors: KRISHNA PARAT, RICHARD FASTOW
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Publication number: 20190043591Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.Type: ApplicationFiled: December 8, 2017Publication date: February 7, 2019Inventors: RICHARD FASTOW, XIN SUN, UDAY CHANDRASEKHAR, KRISHNA K. PARAT, CAMILA JARAMILLO, PURVAL S. SULE, ALIASGAR S. MADRASWALA
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Patent number: 9431109Abstract: Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.Type: GrantFiled: January 31, 2014Date of Patent: August 30, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Hagop Nazarian, Richard Fastow
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Patent number: 9362293Abstract: Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.Type: GrantFiled: December 20, 2013Date of Patent: June 7, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Hagop Nazarian, Richard Fastow, Lei Xue
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Patent number: 9142209Abstract: A method and apparatus receive multiple data pattern analysis requests from a controller and substantially simultaneously perform, with multiple data pattern analysis units, multiple data pattern analyses on one or more portions of a data stream.Type: GrantFiled: April 22, 2014Date of Patent: September 22, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Richard Fastow, Qamrul Hasan