Abstract: The present invention relates to a look-up table architecture and to an FPGA comprising the same. The look-up table architecture comprises a registers group comprising a plurality of registers configured to issue register signals, and a programmable logic comprising a plurality of pass gates configured to be controlled at least by the register signals, the registers group and the programmable logic forming a look-up table, wherein the pass gates are placed in a single direction.

Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A?, B, B?); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array,—at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract: The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).

Abstract: The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.

Abstract: A tristate gate includes an output port and at least two transistors. Each of the transistors has at least a first and a second gate configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract: A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array, at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.

Abstract: The invention relates to a charge pump circuit comprising an input node for inputting a voltage to be boosted; an output node for outputting a boosted voltage; a plurality of pumping stages connected in series between the input node and the output node, each pump stage comprising at least one charge transfer transistor, wherein the at least one charge transfer transistor is a double-gate transistor comprising a first gate for turning the transistor on or off according to a first control signal applied to the first gate and a second gate for modifying the threshold voltage of the transistor according to a second control signal applied to the second gate, wherein the first and second control signals have the same phase.

Abstract: A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

Abstract: The invention relates to a charge pump circuit comprising: an input node for inputting a voltage to be boosted; an output node for outputting a boosted voltage; a plurality of pumping stages connected in series between the input node and the output node, each pump stage comprising at least one charge transfer transistor, wherein the at least one charge transfer transistor is a double-gate transistor comprising a first gate for turning the transistor on or off according to a first control signal applied to the first gate and a second gate for modifying the threshold voltage of the transistor according to a second control signal applied to the second gate, wherein the first and second control signals have the same phase.

Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.

Abstract: The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.

Abstract: The present invention relates to a floating body memory cell comprising: a first MOS transistor and a second MOS transistor, wherein at least the second MOS transistor has a floating body; and wherein the first and second MOS transistors are configured such that charges can be moved to/from the floating body of the second MOS transistor via the first MOS transistor.

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.

Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.

Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-down transistors.

Abstract: The present invention relates to a look-up table architecture and to an FPGA comprising the same. The look-up table architecture comprises a registers group comprising a plurality of registers configured to issue register signals, and a programmable logic comprising a plurality of pass gates configured to be controlled at least by the register signals, the registers group and the programmable logic forming a look-up table, wherein the pass gates are placed in a single direction.