Patents by Inventor Richard H. Hopkins
Richard H. Hopkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220075676Abstract: Input on a plurality of attributes of a computing environment is provided to a machine learning module to produce an output value that comprises a risk score that indicates a likelihood of a potential malfunctioning occurring within the computing environment. A determination is made as to whether the risk score exceeds a predetermined threshold. In response to determining that the risk score exceeds a predetermined threshold, an indication is transmitted to indicate that potential malfunctioning is likely to occur within the computing environment. A modification is made to the computing environment to prevent the potential malfunctioning from occurring.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Inventors: James E. Olson, Micah Robison, Matthew G. Borlick, Lokesh M. Gupta, Richard P. Oubre, JR., Usman Ahmed, Richard H. Hopkins
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Publication number: 20220075704Abstract: A machine learning module is trained by receiving inputs comprising attributes of a computing environment, where the attributes affect a likelihood of failure in the computing environment. In response to an event occurring in the computing environment, a risk score that indicates a predicted likelihood of failure in the computing environment is generated via forward propagation through a plurality of layers of the machine learning module. A margin of error is calculated based on comparing the generated risk score to an expected risk score, where the expected risk score indicates an expected likelihood of failure in the computing environment corresponding to the event. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error, to improve the predicted likelihood of failure in the computing environment.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Inventors: James E. Olson, Micah Robison, Matthew G. Borlick, Lokesh M. Gupta, Richard P. Oubre, JR., Usman Ahmed, Richard H. Hopkins
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Patent number: 11200103Abstract: Input on a plurality of attributes of a computing environment is provided to a machine learning module to produce an output value that comprises a risk score that indicates a likelihood of a potential malfunctioning occurring within the computing environment. A determination is made as to whether the risk score exceeds a predetermined threshold. In response to determining that the risk score exceeds a predetermined threshold, an indication is transmitted to indicate that potential malfunctioning is likely to occur within the computing environment. A modification is made to the computing environment to prevent the potential malfunctioning from occurring.Type: GrantFiled: October 26, 2018Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James E. Olson, Micah Robison, Matthew G. Borlick, Lokesh M. Gupta, Richard P. Oubre, Jr., Usman Ahmed, Richard H. Hopkins
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Patent number: 11200142Abstract: A machine learning module is trained by receiving inputs comprising attributes of a computing environment, where the attributes affect a likelihood of failure in the computing environment. In response to an event occurring in the computing environment, a risk score that indicates a predicted likelihood of failure in the computing environment is generated via forward propagation through a plurality of layers of the machine learning module. A margin of error is calculated based on comparing the generated risk score to an expected risk score, where the expected risk score indicates an expected likelihood of failure in the computing environment corresponding to the event. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error, to improve the predicted likelihood of failure in the computing environment.Type: GrantFiled: October 26, 2018Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James E. Olson, Micah Robison, Matthew G. Borlick, Lokesh M. Gupta, Richard P. Oubre, Jr., Usman Ahmed, Richard H. Hopkins
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Publication number: 20200133820Abstract: A machine learning module is trained by receiving inputs comprising attributes of a computing environment, where the attributes affect a likelihood of failure in the computing environment. In response to an event occurring in the computing environment, a risk score that indicates a predicted likelihood of failure in the computing environment is generated via forward propagation through a plurality of layers of the machine learning module. A margin of error is calculated based on comparing the generated risk score to an expected risk score, where the expected risk score indicates an expected likelihood of failure in the computing environment corresponding to the event. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error, to improve the predicted likelihood of failure in the computing environment.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: James E. Olson, Micah Robison, Matthew G. Borlick, Lokesh M. Gupta, Richard P. Oubre, JR., Usman Ahmed, Richard H. Hopkins
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Publication number: 20200133753Abstract: Input on a plurality of attributes of a computing environment is provided to a machine learning module to produce an output value that comprises a risk score that indicates a likelihood of a potential malfunctioning occurring within the computing environment. A determination is made as to whether the risk score exceeds a predetermined threshold. In response to determining that the risk score exceeds a predetermined threshold, an indication is transmitted to indicate that potential malfunctioning is likely to occur within the computing environment. A modification is made to the computing environment to prevent the potential malfunctioning from occurring.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: James E. Olson, Micah Robison, Matthew G. Borlick, Lokesh M. Gupta, Richard P. Oubre, JR., Usman Ahmed, Richard H. Hopkins
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Publication number: 20090220788Abstract: Adsorbed gaseous species and elements in a carbon (C) powder and a graphite crucible are reduced by way of a vacuum and an elevated temperature sufficient to cause reduction. A wall and at least one end of an interior of the crucible is lined with C powder purified in the above manner. An Si+C mixture is formed with C powder purified in the above manner and Si powder or granules. The lined crucible is charged with the Si+C mixture. Adsorbed gaseous species and elements are reduced from the Si+C mixture and the crucible by way of a vacuum and an elevated temperature that is sufficient to cause reduction but which does not exceed the melting point of Si. Thereafter, by way of a vacuum and an elevated temperature, the Si+C mixture is caused to react and form polycrystalline SiC.Type: ApplicationFiled: December 7, 2006Publication date: September 3, 2009Applicant: II-VI INCORPORATEDInventors: Donovan L. Barrett, Jihong Chen, Richard H. Hopkins, Carl J. Johnson
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Publication number: 20080190355Abstract: The invention relates to substrates of semi-insulating silicon carbide used for semiconductor devices and a method for making the same. The substrates have a resistivity above 106 Ohm-cm, and preferably above 108 Ohm-cm, and most preferably above 109 Ohm-cm, and a capacitance below 5 pF/mm2 and preferably below 1 pF/mm2. The electrical properties of the substrates are controlled by a small amount of added deep level impurity, large enough in concentration to dominate the electrical behavior, but small enough to avoid structural defects. The substrates have concentrations of unintentional background impurities, including shallow donors and acceptors, purposely reduced to below 5·1016 cm?3, and preferably to below 1·1016 cm?3, and the concentration of deep level impurity is higher, and preferably at least two times higher, than the difference between the concentrations of shallow acceptors and shallow donors.Type: ApplicationFiled: July 6, 2005Publication date: August 14, 2008Applicant: II-VI INCORPORATEDInventors: Jihong Chen, Ilya Zwieback, Avinash K. Gupta, Donovan L. Barrett, Richard H. Hopkins, Edward Semenas, Thomas A. Anderson, Andrew E. Souzis
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Patent number: 6056820Abstract: Pure silicon feedstock is melted and vaporized in a physical vapor transport furnace. In one embodiment the vaporized silicon 46 is reacted with a high purity carbon member 74, such as a porous carbon disc, disposed directly above the silicon. The gaseous species resulting from the reaction are deposited on a silicon carbide seed crystal 50 axially located above the disc, resulting in the growth of monocrystalline silicon carbide 56. In another embodiment, one or more gases, which may include a carbon-containing gas, are additionally introduced at 84 into the furnace, such as into a reaction zone above the disc, to participate in the growth process.Type: GrantFiled: July 10, 1998Date of Patent: May 2, 2000Assignee: Northrop Grumman CorporationInventors: Vijay Balakrishna, Godfrey Augustine, Walter E. Gaida, R. Noel Thomas, Richard H. Hopkins
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Patent number: 5985024Abstract: Method and apparatus for growing semiconductor grade silicon carbide boules (84). Pure silicon feedstock (36) is melted and vaporized. The vaporized silicon is reacted with a high purity carbon-containing gas (64), such as propane, and the gaseous species resulting from the reaction are deposited on a silicon carbide seed crystal (50), resulting in the growth of monocrystalline silicon carbide.Type: GrantFiled: December 11, 1997Date of Patent: November 16, 1999Assignee: Northrop Grumman CorporationInventors: Vijay Balakrishna, R. Noel Thomas, Godfrey Augustine, Richard H. Hopkins, H. McDonald Hobgood
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Patent number: 5968261Abstract: An apparatus for growing single-polytype, single crystals of silicon carbide utilizing physical vapor transport as the crystal growth technique. The apparatus has a furnace which has a carbon crucible with walls that border and define a crucible cavity. A silicon carbide source material provided at a first location of the crucible cavity, and a monocrystalline silicon carbide seed is provided at a second location of the crucible cavity. A heat path is also provided in the furnace above the crucible cavity. The crucible has a stepped surface that extends into the crucible cavity. The stepped surface has a mounting portion upon which the seed crystal is mounted. The mounting portion of the stepped surface is bordered at one side by the crucible cavity and is bordered at an opposite side by the furnace heat path. The stepped surface also has a sidewall that is bordered at one side by and surrounds the furnace heat path.Type: GrantFiled: April 21, 1997Date of Patent: October 19, 1999Assignee: Northrop Grumman CorporationInventors: Donovan L. Barrett, Raymond G. Seidensticker, deceased, Richard H. Hopkins
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Patent number: 5937317Abstract: A nitrogen doped single crystal silicon carbide boule is grown by the physical vapor transport process by introducing nitrogen gas into the growth furnace. During the growth process the pressure within the furnace is maintained at a constant value, P.sub.o, where P.sub.o .ltoreq.100 Torr. This is accomplished by measuring the pressure within the furnace and providing the pressure measurement to a process controller which regulates the nitrogen introduction as nitrogen gas is incorporated into the crystal structure. The partial pressure of the nitrogen may be selected to be at a value between 1 and P.sub.o. If the desired partial pressure is less than P.sub.o, an inert gas is added to make up the difference.Type: GrantFiled: May 8, 1997Date of Patent: August 10, 1999Assignee: Northrop Grumman CorporationInventors: Donovan L. Barrett, Richard H. Hopkins, James P. McHugh, Hudson McDonald Hobgood
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Patent number: 5873937Abstract: A method of growing 4-H polytype silicon carbide crystals in a physical vapor transport system where the surface temperature of the crystal is maintained at less than about 2160.degree. C. and the pressure inside the PVT system is decreased to compensate for the lower growth temperature.Type: GrantFiled: May 5, 1997Date of Patent: February 23, 1999Assignee: Northrop Grumman CorporationInventors: Richard H. Hopkins, Godfrey Augustine, H. McDonald Hobgood
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Patent number: 5788768Abstract: A silicon carbide feedstock charge for growing silicon carbide boules in a physical vapor transport system. The feedstock charge includes silicon carbide particles, as well as any dopant material, if required, in a structure which is rigid and self supportable. An elongated feedstock charge may be moved toward the seed crystal as the feedstock is depleted during boule growth. The feedstock charge may be tailored to provide a non-uniform flux for growing more planar boule faces.Type: GrantFiled: May 8, 1997Date of Patent: August 4, 1998Assignee: Northrop Grumman CorporationInventors: Donovan L. Barrett, Richard H. Hopkins
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Patent number: 5746827Abstract: A method for producing crystals of silicon carbide in a furnace. The furnace has a crucible with a cavity in which the cavity has first and second spaced-apart regions. The crucible cavity of the furnace is capable of being heated, preferably by induction or resistance heating, with insulation placed around the crucible and crucible cavity. A source material of silicon carbide is provided at the first region of the crucible cavity, and a monocrystalline seed is placed at the second region of the crucible cavity. A first growth stage is then conducted in which the first region and the second region of the crucible cavity are heated to at least the sublimation temperature of silicon carbide under substantially isothermal conditions. Then, a second growth stage is conducted in which a temperature gradient is provided between the first and the second region of the crucible cavity, such that the seed in the second crucible region is kept at a temperature lower than a temperature of the first crucible region.Type: GrantFiled: December 27, 1995Date of Patent: May 5, 1998Assignee: Northrop Grumman CorporationInventors: Donovan L. Barrett, Richard N. Thomas, Raymond G. Seidensticker, deceased, Richard H. Hopkins
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Patent number: 5683507Abstract: An apparatus for growing single-polytype, single crystals of silicon carbide utilizing physical vapor transport as the crystal growth technique. The apparatus has a furnace which has a carbon crucible with walls that border and define a crucible cavity. A silicon carbide source material provided at a first location of the crucible cavity, and a monocrystalline silicon carbide seed is provided at a second location of the crucible cavity. A heat path is also provided in the furnace above the crucible cavity. The crucible has a stepped surface that extends into the crucible cavity. The stepped surface has a mounting portion upon which the seed crystal is mounted. The mounting portion of the stepped surface is bordered at one side by the crucible cavity and is bordered at an opposite side by the furnace heat path. The stepped surface also has a sidewall that is bordered at one side by and surrounds the furnace heat path.Type: GrantFiled: September 5, 1995Date of Patent: November 4, 1997Assignee: Northrop Grumman CorporationInventors: Donovan L. Barrett, Raymond G. Seidensticker, deceased, Richard H. Hopkins
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Patent number: 5611955Abstract: A substrate for use in semiconductor devices, fabricated of silicon carbide and having a resistivity of greater than 1500 Ohm-cm. The substrate being characterized as having deep level impurities incorporated therein, wherein the deep level elemental impurity comprises one of a selected heavy metal, hydrogen, chlorine and fluorine. The selected heavy metal being a metal found in periodic groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB.Type: GrantFiled: October 18, 1993Date of Patent: March 18, 1997Assignee: Northrop Grumman Corp.Inventors: Donovan L. Barrett, Hudson M. Hobgood, James P. McHugh, Richard H. Hopkins
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Patent number: 5077239Abstract: A crystal of a composition of silver, thallium, and sulfur is useful in non-linear optical devices, acousto-optical devices, piezo electric devices and other types of optical and acoustic devices. The chalcogenide glass composition of the invention displays superior transmission beyond 12 .mu.m.Type: GrantFiled: January 16, 1990Date of Patent: December 31, 1991Assignee: Westinghouse Electric Corp.Inventors: Narsingh B. Singh, Richard H. Hopkins, Walter E. Gaida, Robert Mazelsky
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Patent number: 5043631Abstract: A thin film electroluminescent edge emitter assembly includes a substrate layer having a configuration to define at least one lateral edge surface and at least one integrated circuit formed therein. The integrated circuit has an input for receiving logic signals, and has an excitation voltage input and a plurality of output leads. The output leads form control electrodes each having an end portion terminating at the substrate lateral edge surface. The integrated circuit is operable to provide an excitation voltage to selected control electrodes in response to preselected logic signals provided to the integrated circuit at the logic signal input.A laminar arrangement formed from a first dielectric layer, a second dielectric layer, a phosphor layer interposed between the first and second dielectric layers and a common electrode layer is disposed on the end portions of the control electrodes.Type: GrantFiled: August 23, 1988Date of Patent: August 27, 1991Assignee: Westinghouse Electric Corp.Inventors: Zoltan K. Kun, Michael W. Cresswell, Richard H. Hopkins
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Patent number: 5004956Abstract: A thin film electroluminescent edge emitter assembly includes a substrate layer having a configuration to define at least one lateral edge surface and at least one integrated circuit formed therein. The integrated circuit has an input for receiving logic signals, and has an excitation voltage input and a plurality of output leads. The output leads form control electrodes each having an end portion terminating at the substrate lateral edge surface. The integrated circuit is operable to provide an excitation voltage to selected control electrodes in response to preselected logic signals provided to the integrated circuit at the logic signal input. A laminar arrangement formed from a first dielectric layer, a second dielectric layer, a phosphor layer interposed between the first and second dielectric layers and a common electrode layer is disposed on the end portions of the control electrodes.Type: GrantFiled: November 18, 1988Date of Patent: April 2, 1991Assignee: Westinghouse Electric Corp.Inventors: Zoltan K. Kun, Michael W. Cresswell, Richard H. Hopkins