Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A method and an apparatus providing a circuit edit structure to an integrated circuit enabling circuit edits to be performed through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in the substrate of a flip-chip packaged integrated circuit die. A plurality of contacts couple the passive diffusion to a signal line disposed in a dielectric isolation layer of the integrated circuit die. In another embodiment, the signal line includes an uninterrupted length of approximately 3.0 microns beneath a field oxide region in the integrated circuit die, which provides a circuit edit cut location. The passive diffusion and circuit edit cut locations may be accessed through the back side of the flip-chip packaged integrated circuit, which enable circuit edits to be performed on the flip-chip packaged integrated circuit.

Abstract: A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.

Abstract: A method and an apparatus for editing an integrated circuit. In one embodiment, an integrated circuit substrate is placed into a laser chemical vapor deposition (LCVD) tool and a conductive metal film is deposited onto the integrated circuit substrate over an area of interest. The integrated circuit substrate is subsequently placed into a focused ion beam (FIB) tool where an optional FIB cleaning step is performed on the conductive element deposited by the LCVD tool to help ensure that a good electrical contact can be made. The FIB tool is also used to introduce any desired cuts into signal lines of the integrated circuit to complete edits. The FIB is also used to remove passivation over integrated circuit nodes of interest to expose buried metal lines for subsequent coupling to the conductive element deposited with the LCVD tool.

Abstract: A method and an apparatus providing a circuit edit structure to an integrated circuit enabling circuit edits to be performed through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in the substrate of a flip-chip packaged integrated circuit die. A plurality of contacts couple the passive diffusion to a signal line disposed in a dielectric isolation layer of the integrated circuit die. In another embodiment, the signal line includes an uninterrupted length of approximately 3.0 microns beneath a field oxide region in the integrated circuit die, which provides a circuit edit cut location. The passive diffusion and circuit edit cut locations may be accessed through the back side of the flip-chip packaged integrated circuit, which enable circuit edits to be performed on the flip-chip packaged integrated circuit.

Abstract: A method and an apparatus for performing circuit edits through the back side of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. Next, an insulating layer is deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the insulating layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited insulating layer from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: An apparatus is disclosed. In one embodiment, the apparatus includes a semiconductor substrate and a second substrate. The semiconductor substrate has a top side and a bottom side. The semiconductor substrate has an integrated circuit and at least one alignment fiducial formed on the top side. The alignment fudicial is aligned with the integrated circuit and the alignment fiducial is accessible from the bottom side. The semiconductor substrate further includes a first set of bond pads on the integrated circuit, the bond pads on the top side. The second substrate has a second set of bond pads corresponding to the first set of bond pads. The semiconductor substrate is coupled to the second substrate at a plurality of solder interconnections disposed between the first and the second set of bond pads.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A method and an apparatus for probing signals from an integrated circuit through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in a semiconductor substrate of a flip-chip mounted integrated circuit die. The passive diffusion is coupled to a signal line through a contact. The signal line carries the integrated circuit signal of interest. In one embodiment, the disclosed passive diffusion is oversized to reduce attenuation of a signal acquired from the passive diffusion. In addition, the disclosed passive diffusion is laterally spaced from nearby diffusions in the semiconductor substrate of the integrated circuit to enable exposure of the passive diffusion with a reduced risk of damaging nearby structures in the integrated circuit die, such as for example other diffusions, during the exposing process. Moreover, the disclosed passive diffusion is laterally spaced from nearby diffusions to reduce crosstalk interference from the nearby diffusions.

Abstract: A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure.

Abstract: A method and an apparatus providing a mechanical probe structure through the back side of an integrated circuit die. In one embodiment, semiconductor substrate is thinned from the back side of the integrated circuit die above a probe target. The probe target is then exposed and a thin insulating layer is formed over the exposed probe target and the nearby semiconductor substrate. The thin insulating layer provides electrical isolation between the exposed probe target and the bulk semiconductor substrate. The thin insulating layer also provides a base insulating platform for a probe pad that is subsequently deposited. After the insulating layer is formed over the exposed probe target and the nearby semiconductor substrate, the probe target is re-exposed through insulating layer such that a probe pad may be deposited over the probe target to provide electrical contact to the original probe target as well as provide a probe pad for mechanical probing purposes from the back side of the integrated circuit die.

Abstract: A method for accessing a portion of an integrated circuit formed on top of a semiconductor substrate from the bottom of the semiconductor substrate. First, alignment marks are located which are approximately aligned to the integrated circuit. These alignment marks are then used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access. Finally, an opening is etched into the bottom of the semiconductor substrate at this point.

Abstract: A method and an apparatus for endpoint determination when milling an integrated circuit disposed in a substrate. In one embodiment, the substrate is charged to a first polarity while the well regions and active diffusion regions of the integrated circuit are charged to another polarity thus resulting in an electrical bias at the P-N junctions in the substrate. By powering up the integrated circuit in this fashion during milling, endpoint detection can be accurately determined by using a voltage contrast mechanism such as the imaging detector of a focused ion beam (FIB) milling tool. A diffusion boundary can also be determined in accordance with the teachings of the invention by the use of the stage current monitor of the FIB milling tool.

Abstract: A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure.

Abstract: A method and an apparatus for performing circuit edits through the back side of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. Next, an insulating layer is deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the insulating layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited insulating layer from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: An integrated circuit device having alignment marks that are located on the integrated circuit device semiconductor substrate and aligned to the integrated circuit. The alignment marks are used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access.