Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the sec

Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

Abstract: Described is a fan assembly comprising a body comprising an inlet, an outlet, and means for generating an air flow. The fan assembly also comprises a nozzle mountable on the body for receiving the air flow from the body and for emitting the air flow and a nozzle retaining means for releasably retaining the nozzle on the body. The nozzle retaining means has a first configuration in which the nozzle is retained on the body and a second configuration in which the nozzle is released for removal from the body. The fan assembly also comprises a manually actuable member located on the nozzle for effecting movement of the nozzle retaining means from the first configuration to the second configuration.

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: Described is a fan assembly comprising a body comprising an inlet, an outlet, and means for generating an air flow. The fan assembly also comprises a nozzle mountable on the body for receiving the air flow from the body and for emitting the air flow and a nozzle retaining means for releasably retaining the nozzle on the body. The nozzle retaining means has a first configuration in which the nozzle is retained on the body and a second configuration in which the nozzle is released for removal from the body. The fan assembly also comprises a manually actuable member located on the nozzle for effecting movement of the nozzle retaining means from the first configuration to the second configuration.

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.