Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions. The capability of performing addition or subtraction as the result of comparison permits non-restoring division to be done using a plurality of the linear combining apparatuses.

Abstract: Arbitrary interior surfaces of a three-dimensional body are displayed from a regular array of values of at least one physical property in the interior of the body. The physical property measurements may be made with systems such as computerized tomographic x-ray, or magnetic resonance imaging. Highly parallel circuits and a highly parallel architecture permit generation of surface views in real time, i.e., sufficiently fast to support ongoing procedures such as surgical operations. These parallel circuits, realizable on large scale integrated circuit chips, perform surface normal calculations, linear interpolations and signal comparisons in simultaneously operating circuit paths which are asynchronously enabled when input data appear.

Abstract: The discrete Fourier transform is continuously calculated at input signal sample rate using recursive filtering, rather than transversal filtering. This reduces the number of complex digital multiplications per computational cycle to N, the number of spectral components in the discrete Fourier transform, where rectangular truncation window or a new exponential window is used. Where a triangular truncation window is used the number of complex digital multiplications per computational cycle is reduced to 2N.

Abstract: A design methodology for digit serial architecture, especially for use in digital signal processing circuitry, includes a cell stack configuration incorporating a variable number of individual operation cells in conjunction with cap and control cells to provide power, control and timing signals. The arrangement employed permits the construction of cell libraries for silicon compilers from a small number of individual components and permits such compilers to generate chip fabrication masks for a plurality of fixed, but initially arbitrary digit size circuit designs.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: A cell module which is particularly employable in bit-serial silicon compilation methods permits the fabrication and layout of bit-serial multipliers having variable word sizes. In particular, the cell module permits the fabrication of a bit-serial multiplier which is capable of a number of different functions including the production of high-order (major) and low-order (minor) output product bit streams which may be selected from so as to provide output results in a variety of different formats associated with binary fractional multiplication.

Abstract: A digital multiplier for multiplying together W-bit digit-serial multiplier and multiplicand signals includes a combinational array of multiplier cells arranged in N rows and W columns. A digit-serial-in/parallel-out register supplies respective bits of each successive multiplicand signal to the W columns of the array, the N rows of which receive respective bits of each successive digit of the multiplier signal. After each earlier digit of the multiplier is processed, the carry and sum bits are forwarded without column shift and with one column shift, respectively, from the final row to the first row of multiplier cells. This scrolls the operation of the W-column-by-N-row multiplier cell array, allowing it to be used M times for each word of the multiplier signal, one for each of the M digits in a W-bit word of the multiplier signal.

Abstract: A data shifter is constructed in monolithic integrated-circuit form essentially from three basic cells, namely: a first or A type of bit-slice cell with a multiplexer for selecting one of two inputs to a clocked output latch, a second or B type of bit-slice cell with a multiplexer for selecting one of two inputs to a cascaded pair of clocked latches, and a control cell for controlling the selection process in bit-slice cells arranged in a stack therewith. In addition where the order of the bits in each successive digit of the shifter output needs to be rotated, this can be accomplished using combinations of two further types of basic cells, namely: a braid-slice cell, and a braid-cap cell. These cells are rectangular and tile in a close-packed mosaic. The disclosure describes how to make a same set of basic cells that is adaptable for use both in left shifters and in right shifters.

Abstract: A double precision, low-latency two's complement bit-serial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a stage that it may be completed with a single counter. The multiplier comprises a plurality of bit slices and an endcell connected in series. The serial bit streams of the operands are sampled by latches in each of the bit slices, and the sampled bit values are accumulated using (5,3) counters to generate partial sum output signals. The partial sum output signal for the last bit slice is the least significant word of the double precision product. The endcell comprises another (5,3) counter which accumulates propagated sum and carry output signals of the bit slices and generates the most significant word of the double precision product.