Abstract: Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.

Abstract: The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers.

Abstract: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

Abstract: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate is adjusted to a temperature of no less than about 400° C. and hydrogen gas is excited to form a hydrogen plasma of excited H and H2 species. The photoresist is subjected to the excited H and H2 species from the hydrogen plasma.

Abstract: Semiconductor device structures and related fabrication methods are provided herein. One fabrication method relates to the formation of conductive contact plugs for a semiconductor device. The method begins by providing a semiconductor device structure having a conductive contact region, a layer of insulating material overlying the conductive contact region, and a via formed in the layer of insulating material and terminating at the conductive contact region. The fabrication process then deposits a first electrically conductive material on the semiconductor device structure such that the first electrically conductive material at least partially fills the via. Then, the process anisotropically etches a portion of the first electrically conductive material located in the filled via, resulting in a lined via. Thereafter, the process deposits a second electrically conductive material on the semiconductor device structure such that the second electrically conductive material at least partially fills the lined via.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate.

Abstract: The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers.

Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.

Abstract: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

Abstract: A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.

Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Abstract: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate is adjusted to a temperature of no less than about 400° C. and hydrogen gas is excited to form a hydrogen plasma of excited H and H2 species. The photoresist is subjected to the excited H and H2 species from the hydrogen plasma.

Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.

Abstract: An HTTP server is programmed to detect timed-out client requests by inferring states of its client-server connections. These connections, being full-duplex, can each be viewed as including a client-to-server channel and a server-to-client channel. The state of the server-to-client channel can be inferred by examining local server information to determine whether the client-to-server channel is still established. The server processes a request by a client if the inferred state indicates that the server-to-client channel is still established, and the server terminates the client request if the inferred state indicates that the server-to-client channel is no longer established. Consequently, the server does not expend resources by processing timed-out or dead client requests.

Abstract: The present invention is a counter that takes advantage of the speed and implementation of the LFSR counter by utilizing separate digit counters, each digit counter having a period that is a relative prime to the other digit counter periods. The total period will be the product of all the digit counter periods. Since all digits count independently, there is no carry structure between the digits and hence no delay incurred by carry chains. The pseudorandom number counting sequence for each digit still occurs but is ameliorated by the fact that the digital periods are small and can readily be converted to decimal equivalents by table-lookup and residue lookup.

Abstract: The present invention provides a method and apparatus to significantly accelerate the searching process based on the Monte Carlo principle and the lattice model. Specifically, the energy status of a lattice-based protein conformation is evaluated by modeling the folding process through a pipelined digital circuit using a number of state machines. The pipelined digital circuit reduces the time required for the determination of the energy status of a particular conformation and, therefore, significantly accelerates the searching speed for the lowest energy status. The present invention also permits real-time tuning of problem parameters by the experimenter.

Abstract: Exemplary embodiments of the present invention are directed to providing a memory having N write ports, where N is greater than one. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses and having less than N write ports; the memory also includes a second data memory unit having a plurality of storage locations addressable by the range of addresses, the second data memory having less than N write ports. The memory further includes a control unit configured to select among the first and second memory units in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units each with less than N write ports.