Patents by Inventor Richard J. McPartland
Richard J. McPartland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100271064Abstract: An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Inventors: Ross A. Kohler, Richard J. McPartland, Larry Christopher Wall, Wayne E. Werner
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Publication number: 20100238751Abstract: An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.Type: ApplicationFiled: January 30, 2008Publication date: September 23, 2010Applicant: AGERE SYSTEMS INC.Inventors: Richard Bruce Dell, Ross A. Kohler, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner
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Publication number: 20100229035Abstract: In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.Type: ApplicationFiled: October 31, 2007Publication date: September 9, 2010Applicant: AGERE SYSTEMS INC.Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20100182859Abstract: Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.Type: ApplicationFiled: October 29, 2007Publication date: July 22, 2010Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Patent number: 7746692Abstract: A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.Type: GrantFiled: January 31, 2008Date of Patent: June 29, 2010Assignee: Agere Systems Inc.Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Patent number: 7742355Abstract: A technique to reduce refresh power in a DRAM. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Testing the DRAM uses a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory.Type: GrantFiled: December 20, 2007Date of Patent: June 22, 2010Assignee: Agere Systems Inc.Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20100131825Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.Type: ApplicationFiled: April 26, 2007Publication date: May 27, 2010Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Patent number: 7633830Abstract: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.Type: GrantFiled: November 29, 2007Date of Patent: December 15, 2009Assignee: Agere Systems Inc.Inventors: Donald Albert Evans, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner, Ronald James Wozniak
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Patent number: 7613061Abstract: Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions.Type: GrantFiled: November 30, 2007Date of Patent: November 3, 2009Assignee: Agere Systems Inc.Inventors: Ross A. Kohler, Richard J McPartland, Wayne E Werner
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Publication number: 20090196098Abstract: A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20090161459Abstract: A technique to reduce refresh power in a DRAM is disclosed. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Also disclosed is a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: Agere Systems Inc.Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Patent number: 7551512Abstract: A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing the memory cells. The memory circuit further includes at least one global bit line connected to the plurality of memory sub-blocks. The global bit line is time-multiplexed during a given memory cycle such that the global bit line propagates data associated with a first port in the memory circuit during a first portion of the memory cycle, and the global bit line propagates data associated with a second port in the memory circuit during a second portion of the memory cycle.Type: GrantFiled: July 30, 2007Date of Patent: June 23, 2009Assignee: Agere Systems Inc.Inventors: Donald Albert Evans, Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20090141575Abstract: Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20090141580Abstract: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Donald Albert Evans, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner, Ronald James Wozniak
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Publication number: 20090034356Abstract: A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing the memory cells. The memory circuit further includes at least one global bit line connected to the plurality of memory sub-blocks. The global bit line is time-multiplexed during a given memory cycle such that the global bit line propagates data associated with a first port in the memory circuit during a first portion of the memory cycle, and the global bit line propagates data associated with a second port in the memory circuit during a second portion of the memory cycle.Type: ApplicationFiled: July 30, 2007Publication date: February 5, 2009Inventors: Donald Albert Evans, Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20080301526Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
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Publication number: 20080117702Abstract: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.Type: ApplicationFiled: September 25, 2007Publication date: May 22, 2008Applicant: AGERE SYSTEMS INC.Inventors: Matthew R. Henry, Douglas D. Lopata, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner
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Patent number: 7295480Abstract: A device and method is provided for effecting soft repair of semiconductor memory embedded within an integrated circuit. The invention temporarily and in a non-volatile or quasi-non-volatile manner stores data within the structure of the semiconductor chip. This data respects chip performance at a first test point and may be made available directly from the chip at a second test point. In a particular embodiment of the invention, on-chip non-volatile memory is utilized to communicate reconfiguration codes between two testpoints for soft repair of SRAM and DRAM memory. A reconfiguration code generated for the first test point is stored in the on-chip non-volatile memory and read out from that memory at the second test point. Illustratively, the on-chip non-volatile memory is implemented as quasi-non-volatile memory. In a further embodiment, the invention operates to communicate the reconfiguration codes between a single wafer probe testpoint and a package testpoint.Type: GrantFiled: December 18, 2003Date of Patent: November 13, 2007Assignee: Agere Systems IncInventor: Richard J. McPartland
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Patent number: 7002829Abstract: A method and apparatus for opening a fuse formed on a semiconductor substrate. The apparatus comprises a thyristor formed from CMOS device regions and having a one or two control terminals for permitting current to flow through the thyristor into the fuse, for opening the fuse.Type: GrantFiled: September 30, 2003Date of Patent: February 21, 2006Assignee: Agere Systems Inc.Inventors: Ranbir Singh, Richard J. McPartland, Ross A. Kohler
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Patent number: 6661705Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.Type: GrantFiled: January 24, 2003Date of Patent: December 9, 2003Assignee: Agere Systems Inc.Inventors: Richard J. McPartland, Ranbir Singh