Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Abstract: The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Abstract: A method and associated circuitry are disclosed for applying the high column segment voltages needed to erase and program (write) a segmented column flash EEPROM memory. Low voltage CMOS transistors are used for both the read column precharge path and the write/erase data transfer path. Also, the column segment select switch can be constructed of a single, low voltage, n-channel, transistor, rather than two complementary high voltage transistors. All of the above reduces precharge and discharge time, increasing the read speed of the memory. This also eliminates the lengthening of precharge time that occurs as the characteristics of high voltage transistors degrade with age. The present invention provides the additional advantage of eliminating the need to use less reliable high voltage transistors in certain off-pitch circuits needed for write and erase functions, thus increasing overall chip reliability.

Abstract: A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).

Abstract: A method and associated circuitry are disclosed for applying the high column voltage needed to erase and program (write) a flash EEPROM memory. Low voltage CMOS transistors are used for both the read column precharge path and the write/erase data transfer path. This reduces precharge time, increasing the frequency at which the flash memory can be read. This also eliminates the lengthening of precharge time that occurs as the characteristics of high voltage transistors degrade with age. The present invention provides the additional advantage of eliminating the need to use less reliable high voltage transistors in certain off-pitch circuits needed for write and erase functions, thus increasing overall chip reliability.

Abstract: An on-chip processor is used as a controller for burn-in and endurance testing of embedded non-volatile memory. An automated test machine downloads a test program into the non-volatile memory. The downloaded program contains a test program to be run on the non-volatile memory. When the burn-in or endurance test equipment activates the processor, the processor executes the program and performs a test on the non-volatile memory. The same method can be utilized to perform either the burn-in or endurance tests. Only the clock and reset lines are required to operate the test. Since the clock and reset lines are part of the processor's standard inputs, the method performs burn-in and endurance testing of an embedded non-volatile memory without bringing out the memory's address, data and control lines to the package pins of the integrated circuit.

Abstract: There is disclosed a digital-to-analog converter including a resistor string having intermediate taps at resistor junctions as well as resistor-potential junctions. Switching transistors are coupled between a respective intermediate tap and an output node. Decode circuits are capable of switching at least two transistors to be in the on state at the same time to electrically couple more than one intermediate tap to the output node to produce at least one analog output. In one embodiment, one row select line can be energized simultaneously with at least two column select lines. Alternatively, at least two row select lines can be energized simultaneously with one column select line. A DAC in accordance with the present invention is suitable for fabrication in the form of a monolithic integrated circuit and requires less area while maintaining the same degree of resolution as prior art DACs. The DAC also may be used with successive approximation circuitry to provide an analog-to-digital converter.

Abstract: An integrated circuit is disclosed that includes a sense amplifier having first and second transistors, each of which have a conduction path and a gate electrode. The conduction path of the first and second transistors are electrically coupled in series between a power supply node and an input. The integrated circuit also includes third and fourth transistors each having a conduction path and a gate electrode. The conduction path of the third and fourth transistors are electrically coupled in series between the power supply node and a first reference potential. The gate electrodes of the first and third transistors are electrically coupled to an output node. A fifth transistor has a conduction path electrically coupled between a second reference potential and the output node. The gate electrode is maintained at a voltage that is about two threshold voltage drops below the voltage level of the power supply node.

Abstract: There is disclosed an integrated circuit including a resistive material runner resistor string comprising a series of resistors in which each resistor includes at least one runner direction change feature. Each resistor includes first and second contiguous elements. The junction of the first and second elements form a direction change feature such as a corner in the runner of the resistor string. Taps are positioned along the resistor string at substantially equal resistance intervals. The first and second elements may be squares of different edge dimensions. The resistor string is useful in applications such as digital-to-analog converters.

Abstract: The integrated circuit includes a plurality of row decoder-driver circuits, each for raising the voltage of a respective row line. Each of the plurality of row decoder-driver circuits includes an address decoder capable of receiving a plurality of address bits. The plurality of address bits, when decoded, identify one of the plurality of row decoder-drivers to provide an output. Each of the plurality of row decoder-drivers has an input transistor having a gate. The input transistor has a conduction path coupled between a power supply node and the address decoder. A signal generating circuit receives a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit. The signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits.

Abstract: A high voltage circuit for an electronic erasable programmable read only memory (EEPROM) integrated circuit (IC) is implemented using lower voltage semiconductor components. In the preferred embodiment, the circuit is capable of switching a twenty-four volt signal using p-channel metal-oxide semiconductor field effect transistors (MOSFETs) with a rated breakdown voltage not exceeding twelve volts. In the preferred embodiment, the circuit switches a driver signal in response to a first control signal.