Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.

Abstract: A memory device having a wear out counter. The memory device includes at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the block is accessed, the counter is incremented, allowing a memory controller to level usage and to rectify any problems associated with wear out of that block. A method for incrementing the counter is also included.

Abstract: A method, apparatus and computer program for causing a host computer to optimize execution of plural requests for access to plural data storage locations on a rotating disk, included in a disk storage device, based on a rotational position of the disk relative to a position of a read/write head. The host computer stores position information representing a rotational position of the disk, detects whether plural requests are to be executed, and when plural requests are to be executed, optimizes execution of the requests by reordering a sequence of execution of the requests in a manner to reduce a total service time of the requests based on the position information.

Abstract: An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver.

Abstract: A mass storage system. Two or more dissimilar non-volatile storage mediums have the appearance to an operating system of a single device. In an embodiment, the storage mediums are located within a hard disk drive. In a further embodiment, the non-volatile storage medium is block oriented.

Abstract: A mass storage system. Two or more dissimilar non-volatile storage mediums have the appearance to an operating system of a single device. In an embodiment, the storage mediums are located within a hard disk drive. In a further embodiment, the non-volatile storage medium is block oriented.

Abstract: Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.

Abstract: A memory device having a wear out counter. The memory device includes at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the block is accessed, the counter is incremented, allowing a memory controller to level usage and to rectify any problems associated with wear out of that block. A method for incrementing the counter is also included.

Abstract: Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.

Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: A data storage comprises memory having a plurality of memory cells operative to retain data until read. A buffer cooperates, under the control of an address and buffer manager, with the memory to receive data read from the memory cells of a plurality of memory blocks of the memory. Error correction logic is operatively configured to examine the data read from the memory blocks and determine and correct corrupt data thereof. After the data has been processed by the error correction logic, the address and buffer manager enables write circuitry to write-back the select blocks of memory cells with the processed data of the buffer.

Abstract: A memory system with minimal power consumption. The memory system has a disk memory, a non-volatile cache memory and a memory controller. The memory controller manages memory accesses to minimize the number of disk accesses to avoid the power consumption associated with those accesses. The controller uses the cache to satisfy requests as much as possible, avoiding disk access.

Abstract: A memory device having a wear out counter. The memory device comprises at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the block is accessed, the counter is incremented, allowing a memory controller to level usage and to rectify any problems associated with wear out of that block. A method for incrementing the counter is also included.

Abstract: An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be made based on the usage timeframe information.

Abstract: An apparatus and method to reduce the initialization time of a system is disclosed. In one embodiment, the invention stores metadata for data in a cache memory in a partitioned section of a non-volatile storage media. This allows multiple metadata entries to be read in one operation, thereby improving system performance.

Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.

Abstract: A mass storage system. Two or more dissimilar non-volatile storage mediums have the appearance to an operating system of a single device. In an embodiment, the storage mediums are located within a hard disk drive. In a further embodiment, the non-volatile storage medium is block oriented.

Abstract: A low-cost computing device utilizes a fast access mass storage device with microsecond access times for both its mass storage and main memory requirements. The storage device is configured with a DRAM-like memory electrical interface with a special “doorbell” or interrupt capability. Most of the memory in the storage device is configured as conventional mass storage, and the remainder is configured as main memory.

Abstract: Execution time performance of one or more applications that are dynamically loaded for execution post initial loading is improved by invoking selected parts of the one or more applications for execution post initial loading to allow disk locations accessed and the order the disk locations are accessed to load the selected parts of the one or more applications for execution post initial loading to be traced, and in turn, based at least in part on the order the disk locations are accessed, alternate disk locations to be identified to store the selected parts of the one or more applications to reduce time required to load the selected parts of the one or more applications for execution post initial loading.