Abstract: The present invention is directed to an information handling system device for operatively coupling with a device implementing Input/Output (I/O) virtualization for data transmission. The information handling system device may be configured for executing an operating system control program to manage one or more guest operating systems on the information handling system device. The operating system control program may include a paravirtualization driver for formulating a work queue entry according to the I/O virtualization of the device. Data may be transmitted between the one or more guest operating systems and the device via the paravirtualization driver.

Abstract: An adapter card for directing an information handling system (or another device) device to copy one or more data packets buffered in its memory may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with the information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting a data packet between the electronic components and the information handling system device. The adapter card may buffer a data packet according to a particular interface format and/or may include a buffer for storing the data packet. The adapter card may include control logic configured to direct the information handling system device to copy the data packets buffered in the memory of the adapter card.

Abstract: A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.

Abstract: The present invention is directed to an information handling system device for operatively coupling with a device implementing Input/Output (I/O) virtualization for data transmission. The information handling system device may be configured for executing an operating system control program to manage one or more guest operating systems on the information handling system device. The operating system control program may include a paravirtualization driver for formulating a work queue entry according to the I/O virtualization of the device. Data may be transmitted between the one or more guest operating systems and the device via the paravirtualization driver.

Abstract: An adapter card for directing an information handling system (or another device) device to copy one or more data packets buffered in its memory may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with the information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting a data packet between the electronic components and the information handling system device. The adapter card may buffer a data packet according to a particular interface format and/or may include a buffer for storing the data packet. The adapter card may include control logic configured to direct the information handling system device to copy the data packets buffered in the memory of the adapter card.

Abstract: A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.

Abstract: A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: Methods and systems for improving delayed read handling in a loop of delayed commands among a larger set of commands in a queue of commands are disclosed. In general, when commands in a delayed loop are completed out of order, “holes” are left in the command queue. Skipping over such “holes” consumes multiple clock cycles before another command can be issued, as each “hole” must be examined first in order to determine that it no longer contains a valid read command. A loop of delayed read commands can thus be created from among a larger set of commands in a queue of commands with each command entry having a pointer to the next valid command. Valid delayed read commands in the loop of commands can then be processed by automatically advancing between any two valid delayed read commands among the loop of commands. In this manner, the time to advance between any two commands in the delayed read loop is constant and PCI read performance thereof can be dramatically improved.

Abstract: An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.

Abstract: The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data.

Abstract: A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.

Abstract: A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of code so that errors inherent in maintaining duplicate copies of the same RTL code may be eliminated.

Abstract: A method and apparatus for traversing a queue of commands through part or all of the queue by selecting only the commands that need to be reissued. Commands to be reissued are labeled or designated as valid. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.

Abstract: A method and apparatus in a data processing system for mimicking a device attached to a bus. Signaling is detected on the bus indicating a request to access the device. The bus is then monitored for a response by the device. If a selected period of time passes without a response being made by the device, a response suitable to indicate the presence of the device is sent onto the bus.

Abstract: The present invention is directed to a system and method for tuning retry performance of read requests of data from electronic data storage devices. In an aspect of the present invention, a method for performing a delayed read in an electronic data storage system having an initiator and a target device may include initiating a delayed read by the initiator to the target device and issuing at least one delayed read. The initiator then delays for a programmed interval before reissuing the at least one delayed read.

Abstract: Methods and systems for improving delayed read handling in a loop of delayed commands among a larger set of commands in a queue of commands are disclosed. In general, when commands in a delayed loop are completed out of order, “holes” are left in the command queue. Skipping over such “holes” consumes multiple clock cycles before another command can be issued, as each “hole” must be examined first in order to determine that it no longer contains a valid read command. A loop of delayed read commands can thus be created from among a larger set of commands in a queue of commands with each command entry having a pointer to the next valid command. Valid delayed read commands in the loop of commands can then be processed by automatically advancing between any two valid delayed read commands among the loop of commands. In this manner, the time to advance between any two commands in the delayed read loop is constant and PCI read performance thereof can be dramatically improved.

Abstract: A method and apparatus for traversing a queue of commands through part or all of the queue by selecting only the commands that need to be reissued. Commands to be reissued are labeled or designated as valid. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: The present invention provides a system and method for utilizing a camcorder as a tape backup device for a computing system. A communicative link is established between a camcorder and a computing system which allows data from the computing system to be communicated to the camcorder. The data, once received by the camcorder, is stored in a storage medium of the camcorder.

Abstract: A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of code so that errors inherent in maintaining duplicate copies of the same RTL code may be eliminated.