Abstract: Systems for controlling the current consumption of an integrated circuit chip and the like so as to reduce the inductive voltage drops occurring over the power supply lines within the chip and power supply lines to the chip are disclosed. The systems according to the present invention are applicable to circuits having two or more sub-circuits formed on a semiconductor substrate, each sub-circuit having two or more power supply inputs. An exemplary system comprises two or more current shunting elements formed on the substrate, with each current shunting element coupled in parallel with the power supply inputs of a selected sub-circuit. The system has at least two main power supply lines formed on the semiconductor substrate, with each selected sub-circuit having each of its power supply inputs coupled to a main power supply line. A current shunting element may comprise a Zener diode, an active shunt circuit, or equivalents thereof.

Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer.

Abstract: A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included.

Abstract: A multi-layer printed wiring board design method employs establishing of critical and non-critical signal layers with first and second design rule sets assigned respectively. A configuration employing y x y' layers wherein conductors in the y and y' layers are orthogonal to x layers and y' layers are offset by approximately one-half pitch from y layers for cross talk reduction.

Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer.

Abstract: An electronic component assembly and method for enhancing density and operational speed. The assembly includes a plurality of integrated circuit chips which are mounted to a planar surface of a substrate, preferably a printed circuit board, with the opposed major faces of the chips being perpendicular to the planar surface. One of the major faces of each chip is the active face having a pattern of signal pads. The pads are disposed along the face periphery adjacent to the edge of the chip contacting the printed circuit board. The signal pads have solder bumps which can be soldered directly to contact pads on the printed circuit board. A passivating edge-coating on each chip protects the chip and prevents electrical shorting on the printed circuit board. A source of fluid directs a cooling flow along the large area major surfaces of the chips.

Abstract: A digital signalling circuit employs a spaced apart driver and receiver pair in which the signal current originates at the receiver and is constant in time. The receiver chip includes a constant current source connected to the power supply plane and one termination of a signal line, a termination resistor connected across the signal line termination to the ground plane, and a sense amplifier connected to the signal line termination for sensing the voltage level or the signal line. The driver chip comprises a single switching transistor connected across the opposite end of the signal line to the ground plane, and is not directly coupled to the power supply plane. When the driver switching transistor is on, the signal line is grounded and the termination resistor in the receiver is effectively shorted out. When the driver switching transistor is turned off, the signal source current at the receiver charges up the signal line and develops a voltage across the termination resistor.