Abstract: A system and method for protocol independent receive side scaling (RSS) includes storing a plurality of RSS hash M-tuple definitions, each definition corresponding to one of a set of possible protocol header combinations for routing an incoming packet, the set of possible protocol header combinations being modifiable to include later-developed protocols. Based on initial bytes of the incoming packet, a pattern of protocol headers is detected, and used to select one of the plurality of RSS hash M-tuple definitions. The selected RSS hash M-tuple definition is applied as a protocol-independent arbitrary set of bits to the headers of the incoming packet to form a RSS hash M-tuple vector, which is used to compute a RSS hash. Based on the RSS hash, a particular queue is selected from a set of destination queues identified for the packet, and the packet is delivered to the selected particular queue.

Abstract: A system and method for protocol independent multi-flow table routing includes a first flow table, a second flow table, and a shared hash table accessible by both the first flow table and the second flow table. Upon receipt of a packet, a first secure signature of a first lookup key is generated for the first flow table, and a second secure signature of a second lookup key is generated for the second flow table. The shared hash table stores both the first secure signature in association with a first value corresponding to the first secure signature, and the second secure signature along with a second value corresponding to the second secure signature. The first and second values indicate destination information for the packet.

Abstract: A system and method for protocol independent receive side scaling (RSS) includes storing a plurality of RSS hash M-tuple definitions, each definition corresponding to one of a set of possible protocol header combinations for routing an incoming packet, the set of possible protocol header combinations being modifiable to include later-developed protocols. Based on initial bytes of the incoming packet, a pattern of protocol headers is detected, and used to select one of the plurality of RSS hash M-tuple definitions. The selected RSS hash M-tuple definition is applied as a protocol-independent arbitrary set of bits to the headers of the incoming packet to form a RSS hash M-tuple vector, which is used to compute a RSS hash. Based on the RSS hash, a particular queue is selected from a set of destination queues identified for the packet, and the packet is delivered to the selected particular queue.

Abstract: The present application describes a system and method for rate limiting traffic of network users, such as virtual machines (VMs). In accordance with the disclosure, transmission queues for the VMs may be assigned to two levels of rate limiting. The first-level rate limit may be an individual rate limit for a particular transmission queue, while the second-level rate limit may be a group rate limit that is applied to a group of transmission queues. The first-level rate limit for some transmission queues may be performed using software rate limiting, while for other transmission queues the first-level rate limit may be performed using hardware rate limiting. The second-level rate limit may be applied to a group of transmission queues that contains both software first-level rate limited transmission queues and hardware first-level rate limited transmission queues.

Abstract: A system and method for protocol independent receive side scaling (RSS) includes storing a plurality of RSS hash M-tuple definitions, each definition corresponding to one of a set of possible protocol header combinations for routing an incoming packet, the set of possible protocol header combinations being modifiable to include later-developed protocols. Based on initial bytes of the incoming packet, a pattern of protocol headers is detected, and used to select one of the plurality of RSS hash M-tuple definitions. The selected RSS hash M-tuple definition is applied as a protocol-independent arbitrary set of bits to the headers of the incoming packet to form a RSS hash M-tuple vector, which is used to compute a RSS hash. Based on the RSS hash, a particular queue is selected from a set of destination queues identified for the packet, and the packet is delivered to the selected particular queue.

Abstract: A system and method for protocol independent multi-flow table routing includes a first flow table, a second flow table, and a shared hash table accessible by both the first flow table and the second flow table. Upon receipt of a packet, a first secure signature of a first lookup key is generated for the first flow table, and a second secure signature of a second lookup key is generated for the second flow table. The shared hash table stores both the first secure signature in association with a first value corresponding to the first secure signature, and the second secure signature along with a second value corresponding to the second secure signature. The first and second values indicate destination information for the packet.

Abstract: The present technology pertains to unilaterally interleaving individual data packets of long bursts of multi-packet messages in various sequence patterns to be sent to one or more receivers over a network. Before determining a pattern, the sending device attempts to reduce the transmission length of the long bursts of the data packets into multiple chunks. Subsequently, the sending device generates a sequence pattern of the individual data packets and consecutively transmits these packets to their respective receivers. The determined sequence pattern may be based upon outbound limits at the sender, inbound limits at the one or more receivers, and various transmission priorities. Moreover, the sender may limit the data flow of any message transmission. The present technology does not require feedback from the network's components or from the network itself to micro flow control the individual data packets.

Abstract: A system and method for protocol independent receive side scaling (RSS) includes storing a plurality of RSS hash M-tuple definitions, each definition corresponding to one of a set of possible protocol header combinations for routing an incoming packet, the set of possible protocol header combinations being modifiable to include later-developed protocols. Based on initial bytes of the incoming packet, a pattern of protocol headers is detected, and used to select one of the plurality of RSS hash M-tuple definitions. The selected RSS hash M-tuple definition is applied as a protocol-independent arbitrary set of bits to the headers of the incoming packet to form a RSS hash M-tuple vector, which is used to compute a RSS hash. Based on the RSS hash, a particular queue is selected from a set of destination queues identified for the packet, and the packet is delivered to the selected particular queue.

Abstract: In one aspect, one or more processors may be coupled to a content-addressable memory, a first memory and a second memory. The one or more processors may be configured to receive a data packet, read a predetermined number of bytes from the data packet, and match the read bytes to patterns corresponding to rows of the content-addressable memory. Further, the one or more processors may determine a number associated with the matched row, and based on the number, determine an initial routing instruction. The one or more processors may then determine which bits of the read bytes to hash using hash information stored in the first memory, hash the bits to generate a hash value, determine whether the value corresponds to routing information in the second memory, and route the data packet based on the routing information.

Abstract: In one aspect, one or more processors may be coupled to a content-addressable memory, a first memory and a second memory. The one or more processors may be configured to receive a data packet, read a predetermined number of bytes from the data packet, and match the read bytes to patterns corresponding to rows of the content-addressable memory. Further, the one or more processors may determine a number associated with the matched row, and based on the number, determine an initial routing instruction. The one or more processors may then determine which bits of the read bytes to hash using hash information stored in the first memory, hash the bits to generate a hash value, determine whether the value corresponds to routing information in the second memory, and route the data packet based on the routing information.

Abstract: The present technology pertains to unilaterally interleaving individual data packets of long bursts of multi-packet messages in various sequence patterns to be sent to one or more receivers over a network. Before determining a pattern, the sending device attempts to reduce the transmission length of the long bursts of the data packets into multiple chunks. Subsequently, the sending device generates a sequence pattern of the individual data packets and consecutively transmits these packets to their respective receivers. The determined sequence pattern may be based upon outbound limits at the sender, inbound limits at the one or more receivers, and various transmission priorities. Moreover, the sender may limit the data flow of any message transmission. The present technology does not require feedback from the network's components or from the network itself to micro flow control the individual data packets.

Abstract: Network device and method for routing a packet and setting up a new flow. The device includes a packet classifier, a field-selection table, a hash module, and a routing table. A packet is routed by finding an entry in the field-selection table using the packet classifier, selecting bits from the packet based on the entry in the field-selection table, and hashing the selected bits along with an identifier from the packet classifier or the field-selection table, using the hash module. The hash result is used to locate instructions in the routing table. When setting up a new flow, the hash module result may point to an existing entry in the routing table. In such instances, a new entry is added to the packet classifier, such that the hash module will produce a different result that points to an available entry in the routing table.

Abstract: Methods for identifying and analyzing performance traces are provided. Temporal logic formulas are patterns that can be compared with traces and individual events to identify the existence of certain behavior. Traces, sequences of time-stamped events in time order, are compared with one or more temporal logic formulas to identify the event sequences that match the formulas. The temporal logic formulas can be written in the simple temporal logic language that is presented. When a formula matches an event sequence, attributes from the event sequence are extracted and metric expressions are evaluated based on these attributes. The extracted attributes and the results of the metric expression are returned. This temporal logic pattern matching process can efficiently identify and analyze performance traces and significantly reduce manual effort for identifying performance problems.

Abstract: A system, method and program product, the system in embodiments comprising: one or more computers operably connected to one or more computer-readable storage media comprising computer-readable program code to perform steps: associating a first plurality of data disk blocks; generating checksum data on a second plurality of checksum disk blocks, using an m-out-of-n encoding algorithm; generating a third plurality of redundant storage disk blocks, using an 1-out-of-n encoding algorithm that allows for reconstruction using a second recovery algorithm of a selected disk block by reading a proper subset of remaining data disk blocks, reconstructing a single one of the data disk blocks when one or more reconstruction criteria are met, using the second recovery algorithm; reconstructing, when two or more of the data disk blocks are lost, the two or more of the data disk blocks and/or checksum disk blocks that are lost, using the first recovery algorithm.

Abstract: A computer device including a transceiver receives broadcasts from cellular sites within a range of the transceiver. The computer device compares the identity of cellular site identifying information received at different periods to determine a transit status of the device and based on the transit status, broadcasts its location.

Abstract: A method is described which compares contents-rich documents page by page and creates a difference document of paired pages. The pages are compared, in that order, based on their marking operators, on bitmaps rendered from the still unpaired pages, and on a subset of the bitmap, e.g. in smaller page areas. Pages that are visually identical are paired. Blank pages are inserted if pages cannot be paired to deal with page insertions and deletions. Differences between pages which can be visible in a printed document, are marked on the paired pages. The method can be used with documents that contain embedded graphical contents as well as with plain text files.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard. sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register.

Abstract: A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.