Abstract: It is not always possible or practical to fully translate an original computer program because execution transfer instructions may have computed destination addresses that cannot be determined until program execution. Instead, a digital computer alternately executes a translated program that is a partial translation of the original computer program, and interprets the original program. When execution of the translated program specifies a transfer to an untranslated portion of the original program, execution is transferred to an interpreter to interpret the original program. When interpretation of the original program reaches a portion of the original program having been translated, execution is transferred to the translated program. In a preferred embodiment, the original program is partially translated by automatically generating a flowgraph, and using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph.

Abstract: A program is translated by automatically generating a flowgraph, using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph, and then using the flowgraph and the information about the blocks of instructions to generate translated instructions. Due to execution transfers to computed destination addresses that are not determined prior to program execution, it is not possible to include all of the program instructions in the flowgraph. Execution transfers to these computed destinations are coded as calls to an interpreter that interprets the untranslated code. Returns are made from the interpreter to block entry points that are the first instructions in the blocks. Moreover, information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during retranslation of the original program.

Abstract: The embodiment relates to special controls in a processor to prevent synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual page addresses in multiple address spaces into real main storage page frame addresses. The controls use a synonym resolution register (SRR) which divides each address space in the system into common and private portions. Fields in the SRR indicate which portions are to be common to all address spaces, and which portions are private in each address space. A SRR control circuit selects a particular status field under control of a virtual address requesting main storage access. Each DLAT entry contains a common/private storage indicator which is controlled by the particular status field when the DLAT entry is loaded.