Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

Abstract: In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Abstract: A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.

Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.

Abstract: A dynamic random access memory device (DRAM) receiver circuit includes an input to receive a data signal, and also includes decision circuitry to make a decision about the received data signal based on a present sampled data signal and a coefficient value corresponding to at least one of a previously sampled data signals.

Abstract: A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

Abstract: A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

Abstract: A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.

Abstract: An integrated circuit device includes an output driver, a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device, and a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver. The output driver is configurable to output data synchronously with respect to an external clock signal.

Abstract: An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device. The value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line. The signals present on the external signal line comprise one selected from residual signals and cross coupled signals.

Abstract: An integrated circuit device includes a transmitting means for transmitting transmit data to an external signal line and a storing means for storing a first value representative of a transmit phase adjustment that is used to adjust when the transmit data is transmitted by the transmitting means. The first value is determined based on information stored in a memory device external to the integrated circuit device.

Abstract: An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.

Abstract: A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.

Abstract: An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.

Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

Abstract: An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

Abstract: A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.

Abstract: A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operation is selected such that the refresh frequency is minimized to conserve power consumed by the memory device while being sufficient to refresh the rows of the memory cells.