Abstract: An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.

Abstract: An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: An integrated circuit implements a transistor mismatch sensor comprising first and second inverter chains coupled to a register. The register comprises a plurality of flip-flops having clock inputs driven by an output of the first inverter chain and data inputs driven by an output of the second inverter chain. Data outputs of the flip-flops of the register are indicative of an amount of mismatch between transistors of different conductivity types in the first and second inverter chains. For example, the register may comprise a thermometer encoded register providing a digital output signal having a first value indicative of an approximate match in speed, drive strength or other characteristics between the transistors of the first and second conductivity types, with values above and below the first value being indicative of respective first and second different types of relative mismatch in speed, drive strength or other characteristics.

Abstract: An integrated circuit implements a transistor aging effects sensor comprising first and second delay lines, each comprising a plurality of delay elements, and a register. The register comprises a plurality of flip-flops having data inputs driven by respective outputs of respective ones of the delay elements of the first delay line and clock inputs driven by one or more clock signals provided by at least one of the delay elements of the second delay line. Data outputs of the flip-flops of the register are indicative of one or more aging effects in transistors of the first and second delay lines. For example, the register may comprise a thermometer encoded register providing digital output signals used to determine aging effects in the transistors of the first and second delay lines. Embodiments can be implemented using differential delay lines or delay lines comprising respective inverter chains.

Abstract: An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.

Abstract: An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.

Abstract: A secure memory system and a method of maintaining the security of memory contents. One embodiment of the system includes: (1) a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place the system in a secure mode, (2) a secure memory bridge coupled to the security control and system memory and configured to encrypt and decrypt data associated with the system memory based on a state of the system memory secure mode signal and (3) a boot processor coupled to the security control module and the secure memory bridge and configured to transmit requests to the secure memory bridge in the secure mode and an unsecure mode.

Abstract: Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.

Abstract: A secure memory system and a method of maintaining the security of memory contents. One embodiment of the system includes: (1) a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place the system in a secure mode, (2) a secure memory bridge coupled to the security control and system memory and configured to encrypt and decrypt data associated with the system memory based on a state of the system memory secure mode signal and (3) a boot processor coupled to the security control module and the secure memory bridge and configured to transmit requests to the secure memory bridge in the secure mode and an unsecure mode.

Abstract: A method of operating an embedded memory having (i) a local memory, (ii) a system memory, and (iii) a multi-level cache memory coupled between a processor and the system memory. According to one embodiment of the method, a two-level cache memory is configured to function as a single-level cache memory by excluding the level-two (L2) cache from the cache-transfer path between the processor and the system memory. The excluded L2-cache is then mapped as an independently addressable memory unit within the embedded memory that functions as an extension of the local memory, a separate additional local memory, or an extension of the system memory.

Abstract: Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.

Abstract: A PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. In one embodiment, the method includes: (1) generating a memory request at a first chip of the printed circuit board, (2) transforming the memory request to a shared memory request and (3) directing the shared memory request to an off-chip shared memory space indirectly coupled to the first chip via a second chip of the printed circuit board.

Abstract: Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.

Abstract: A fully-static dual-voltage sense circuit designed for a mixed-voltage system senses the power-rail voltage of other devices that the device is interfaced with, and achieves a low-power consumption level without software assistance when the sensing circuit is active, and protects low-voltage process devices in the circuit from possible high voltage damage at the interface. In a preferred embodiment, the present invention includes an integrated circuit having a dual-voltage sense circuit, the sense circuit including a sense circuit input node supplied with an input voltage Vin; a sense circuit power input node supplied with a power-supply voltage; and a sense circuit output node outputting a digital signal of a voltage level equal to or less than the voltage level of a low-voltage digital signal, regardless of the voltage level of the input voltage.

Abstract: A computer peripheral device suitable for operation with a Peripheral Component Interconnect (PCI) Bus or the like, has the ability to “wakeup” the bus from a cold state (e.g., D3cold) without the need to supply auxiliary power (e.g., 3.3 volts) to the entire device during the cold state. A modem in the preferred embodiment (although the invention is applicable to other peripheral devices), the device latches device status information from the main circuitry of the device (operating on 5 volts, for example) into a “keep alive” circuit connected to the auxiliary power supply upon the falling edge of a PCI reset signal (RST#). Additionally, the auxiliary power supply also powers a ring detect circuit for the detection of an incoming telephone call, which incoming call triggers a Power Management Event (PME#) signal for changing the state of the bus to an active state.