Abstract: An encoder which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the encoder produces a glitch-free encoded signal.

Abstract: An edge signal restoration circuit and method to enhance an edge of a signal decreases a rise and fall time of a propagating signal during transitions between logic states. The edge signal restoration circuit includes a first circuit to detect an edge of an input signal and to output a detection signal, and a second circuit to drive a next state of the input signal in response to the detection signal at approximately the same time as the first circuit detects the edge of the input signal. The edge signal restoration method detects a transition of the signal between a current state and a next state, and drives the next state onto the signal during its transition to that next state.

Abstract: There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node.

Abstract: A data converter for converting a signal either from analog form to digital form or from digital form to analog form includes a storage register. The storage register receives and temporarily stores digital data samples. The digital data samples are transferable out of the storage register in the same sequence in which they were received. A digital signal processor coupled to the storage register is interruptible to transferred digital data samples either to or from the storage register. In this manner, the digital signal processor transfers multiple digital data samples either to or from the storage register during each interrupt rather than transferring a single data sample per interrupt, thereby reducing the number of interrupts necessary to transfer a given number of digital data samples.

Abstract: An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.

Abstract: An integrated circuit has an oscillator for generating a plurality of phases of an oscillator clock signal. Each phase of the oscillator clock clocks a respective one of a plurality of ring shift registers. The output of each stage of the ring shift registers is a phase of a desired clock signal and is an input to a multiplexer that can selectively provide one of the desired clock phases as the output of the multiplexer. In another embodiment of the invention the ring shift registers generate half of the phases of a desired clock signal at a multiple of the desired frequency. The multiplexer output clocks a divide by two circuit which is followed by another level of multiplexing to generate the other half of the phases and to divide down to the desired frequency.