Abstract: Electromagnetic-energy absorbing materials are combined with thermally conductive materials, such as those used for thermal management in association with electronic equipment, thereby suppressing the transmission of electromagnetic interference (EMI) therethrough. Disclosed are materials and processes for combining EMI-absorbing materials with thermally conductive materials thereby improving EMI shielding effectiveness in an economically efficient manner. In one embodiment, a thermally conductive EMI absorber is prepared by combining an EMI-absorbing material (for example, ferrite particles) with a thermally conducting material (for example, ceramic particles), each suspended within an elastomeric matrix (for example, silicone). In application, a layer of thermally conductive EMI-absorbing material is applied between an electronic device or component, and a heat sink.

Abstract: A Personal Computer Memory Card International Association (PCMCIA) card may establish, via a non-secure network, a secure communications channel between a computer and a secure network. The non-secure network may define a first address space. The secure network may define a second address space. The PCMCIA card may include a cryptography module, a network adapter, and/or a processor. The cryptography module may provide Type 1 cryptography of data communicated between the computer and the secure network. The network adapter may be in communication with the non-secure network and may be associated with a first network address from the first address space. The processor may be in communication with the secure network via the cryptography module and the network adapter. The processor may identify a second network address for the computer from the second address space and may communicate the second network address to the computer, for example via dynamic host control protocol (DHCP).

Abstract: A device that includes a first processor, a second processor, and an encryption module in communication with the first processor and the second processor may be used to accept conditions for access to the network. The first processor may receive condition data, and in response, may send an acceptance signal via the encryption module to the second processor. The second processor may receive the acceptance signal and, in response, may send acceptance data to a gatekeeper. The encryption module may block unencrypted data other than the acceptance signal from being communicated from the first processor to the second processor. The encryption module may support type 1 encryption.

Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Abstract: The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit at the same speed data propagates though the circuit. The cells of the integrated circuit are wavefront clock synchronized in that the phase offset introduced in a particular cell's clock is such that the arrival of a skewed clock and propagation delayed data from that cell's neighbor is synchronized with that particular cell's own clock. Wavefront clock synchronization mitigates at least some of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies associated with large surface integrated circuits utilizing synchronized clock domains.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: Electro-magnetic-energy absorbing materials are used to treat air filters, such as those used in association with electronic equipment thereby suppressing the transmission of electromagnetic interference (EMI) therethrough. Disclosed are processes and materials for applying EMI-absorbing materials to air filters thereby improving EMI-shielding effectiveness in an economically efficient manner. In one embodiment, an absorptive solution is prepared using an absorptive material and a binding agent. A heavy coating of absorbing solution applied to an air filter substrate, for example by dipping or spraying. Excess absorbing material is subsequently removed and the absorbing material cured, such that the passage of air through the filter remains substantially unimpeded. The resulting absorptive air filter is then optionally treated with a flame retardant to meet a predetermined safety standard.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: A connector including a first set of signal conducting members realized at least in part on a first surface and a second set of signal conducting members realized at least in part on a second surface, the second set being remote from the first set. In each set, the signal conducting members are arranged generally side by side. The connector also includes a plurality of connection paths, characterized by a layout for interconnecting the first and second sets of discrete signal conducting members such that signals may be exchanged between signal conducting members of the first and second sets. Specific to the invention, each signal conducting member of the first set is provided with connection paths to a different pair of non-contiguous signal conducting members of the second set.

Abstract: Lossy materials can be used to suppress EMI transmission. Disclosed are methods for applying lossy materials to EMI shielded enclosures to improve EMI shielding effectiveness and the EMI shielded enclosures so produced. In some embodiments, the EMI shielded enclosure includes a printed-circuit board mountable device. In one embodiment, lossy material can be applied to the interior of an EMI shielded enclosure using an adhesive. In another embodiment, lossy materials can be applied to the exterior of the EMI enclosure to suppress EMI incident upon the EMI shielded enclosure, thereby reducing the susceptibility of electronics contained within the EMI shielded enclosure. In yet another embodiment, lossy materials can be applied to both the interior and exterior of the EMI enclosure.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, thereby permitting exchange of data packets between the cells of the array. Each cell includes a memory for holding a plurality of data packets for transmission to other cells of said array. Each data packet of the plurality of data packets has a characteristic element represented by a parameter, the parameter allowing one data packet to be distinguished from another data packet in the plurality of data packets. Each cell further includes a control entity operative to select at least one data packet from the plurality of data packets at least in part on a basis of the parameter and to transmit the selected data packet to another cell of said array of cells.

Abstract: According to one embodiment, the present invention relates to a method and a system for efficient transaction processing.

Abstract: The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit at the same speed data propagates though the circuit. The cells of the integrated circuit are wavefront clock synchronized in that the phase offset introduced in a particular cell's clock is such that the arrival of a skewed clock and propagation delayed data from that cell's neighbor is synchronized with that particular cell's own clock. Wavefront clock synchronization mitigates at least some of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies associated with large surface integrated circuits utilizing synchronized clock domains.

Abstract: Methods and apparatus for processing a plurality of sets of routing information received from corresponding ones of a plurality of neighbor nodes connectable to a router, the router having a plurality of memory units accessible via separate paths. The method comprises creating a respective plurality of non-identical routing information subsets from each of at least one of the received sets of routing information; accessing the plurality of memory units via the separate access paths; and storing the plurality of non-identical routing information subsets created from a given one of said received sets of routing information in respective ones of the plurality of memory units. By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.