Abstract: A method uses natural language for visual analysis of a dataset. A data visualization application displays a data visualization, at a computer, based on a dataset retrieved from a database using a set of one or more queries. A user specifies a natural language command related to the displayed data visualization, and the computer extracts an analytic phrase from the natural language command. The computer computes semantic relatedness between the analytic phrase and numeric data fields in the dataset. The computer identifies numeric data fields having highest semantic relatedness to the analytic phrase, and also selects a relevant numerical function. The numerical function compares data values in the numeric data fields to a threshold value. The computer retrieves an updated dataset that filters the identified numeric data fields according to the numeric function. The computer then displays an updated data visualization using the updated dataset.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof.

Abstract: This invention provides a three-dimensional (3D) junction semiconductor memory device and fabrication method thereof. The 3D junction semiconductor memory device comprises a plurality of vertical channel structures and a plurality of gate layers staked up in a vertical direction. The pluralities of vertical channel structures comprise multiple alternatively stacked source/drain material layers and channel material layers in a vertical direction, and the source/drain material layer comprises p type polysilicon, and the channel material layer comprises n type polysilicon so as to constitute a plurality of junction transistors connected in series vertically, such that not only a smaller component size can be achieved, but also more flexible storage unit operation can be achieved.

Abstract: This invention provides a three-dimensional (3D) junction semiconductor memory device and fabrication method thereof. The 3D junction semiconductor memory device comprises a plurality of vertical channel structures and a plurality of gate layers staked up in a vertical direction. The pluralities of vertical channel structures comprise multiple alternatively stacked source/drain material layers and channel material layers in a vertical direction, and the source/drain material layers and the channel material layers are doped with different doping types so as to constitute a plurality of junction transistors connected in series vertically, such that not only a smaller component size can be achieved, but also more flexible storage unit operation can be achieved.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof.

Abstract: This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Abstract: The present application provides a method for growing monocrystalline silicon by using Czochralski method, comprising: step (1) melting a deuterium-, nitrogen- and barium-doped silicon sheet and a polycrystalline silicon in a crucible; step (2) forming a deuterium- and nitrogen-doped monocrystalline silicon ingot by using magnetic field-applied Czochralski method. The impurity level of the melt and the grown crystal can be reduced according to the present application. By applying rapid thermal annealing to the nitrogen-doped monocrystalline silicon sheet, crystal originated particle defects in surface area of the silicon sheet can be eliminated. The storage of deuterium atoms in gaps of the silicon sheet is able to reduce the contents of oxygen and carbon impurities.

Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Abstract: The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.

Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Abstract: A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.

Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Abstract: This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Abstract: The present invention provides a method for forming a quantum well device having high mobility and high breakdown voltage with enhanced performance and reliability. A method for fabrication of a Vertical Cylindrical GaN Quantum Well Power Transistor for high power application is disclosed. Compared with the prior art, the method of forming a quantum well device disclosed in the present invention has the beneficial effects of high mobility and high breakdown voltage with better performance and reliability.

Abstract: The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.