Patents by Inventor Richard R. Chang
Richard R. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240406686Abstract: Systems and methods for sharing location information during a message conversation are provided. An electronic device displays a message region for displaying a message transcript of messages sent between a first participant and a second participant in a message conversation. In response to detecting a swipe up, the electronic device displays a location-sharing affordance. The electronic device detects a selection of the location-sharing affordance, where detecting a selection of the location-sharing affordance by the first participant comprises detecting a single contact by the first participant. In response to detecting a selection of the location-sharing affordance, the electronic device enables the second participant to obtain the first participant location information.Type: ApplicationFiled: August 13, 2024Publication date: December 5, 2024Inventors: Jae Woo CHANG, Megan M. FROST, Joshua B. DICKENS, Stephen O. LEMAY, Marcel VAN OS, Richard R. DELLINGER, Lawrence Y. YANG
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Patent number: 12131374Abstract: In some embodiments, exemplary user interfaces for provisioning an electronic device with an account are described. In some embodiments, exemplary user interfaces for providing usage information of an account are described. In some embodiments, exemplary user interfaces for providing visual feedback on a representation of an account are described. In some embodiments, exemplary user interfaces for managing the tracking of a category are described. In some embodiments, exemplary user interfaces for managing a transfer of items are described. In some embodiments, exemplary user interfaces for managing an authentication credential connected with an account are described. In some embodiments, exemplary user interfaces for activating a physical account object are described. In some embodiments, exemplary user interfaces for managing balance transfers are described.Type: GrantFiled: April 13, 2023Date of Patent: October 29, 2024Assignee: Apple Inc.Inventors: Marcel Van Os, Stacey R. Abrams, Jae Woo Chang, Steven Eastcott, Jarad M. Fisher, Christine Franco, David T. Haggerty, Richard W. Heard, Mischa McLachlan, Aaron Melim, Ashish C. Nagre, Akila Suresh
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Patent number: 12089121Abstract: Systems and methods for sharing location information during a message conversation are provided. An electronic device displays a message region for displaying a message transcript of messages sent between a first participant and a second participant in a message conversation. The electronic device displays a location-sharing affordance. The electronic device detects a selection of the location-sharing affordance, where detecting a selection of the location-sharing affordance by the first participant comprises detecting a single contact by the first participant. In response to detecting a selection of the location-sharing affordance, the electronic device enables the second participant to obtain the first participant location information and displays a modified location-sharing affordance.Type: GrantFiled: August 11, 2022Date of Patent: September 10, 2024Assignee: Apple Inc.Inventors: Jae Woo Chang, Megan M. Frost, Joshua B. Dickens, Stephen O. Lemay, Marcel Van Os, Richard R. Dellinger, Lawrence Y. Yang
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Patent number: 11049857Abstract: This invention provides a semiconductor device and a manufacturing method thereof.Type: GrantFiled: August 29, 2019Date of Patent: June 29, 2021Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.Inventors: Deyuan Xiao, Richard R. Chang
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Publication number: 20200258902Abstract: This invention provides a three-dimensional (3D) junction semiconductor memory device and fabrication method thereof. The 3D junction semiconductor memory device comprises a plurality of vertical channel structures and a plurality of gate layers staked up in a vertical direction. The pluralities of vertical channel structures comprise multiple alternatively stacked source/drain material layers and channel material layers in a vertical direction, and the source/drain material layers and the channel material layers are doped with different doping types so as to constitute a plurality of junction transistors connected in series vertically, such that not only a smaller component size can be achieved, but also more flexible storage unit operation can be achieved.Type: ApplicationFiled: December 16, 2019Publication date: August 13, 2020Inventors: Deyuan Xiao, Richard R. Chang
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Publication number: 20200258895Abstract: This invention provides a three-dimensional (3D) junction semiconductor memory device and fabrication method thereof. The 3D junction semiconductor memory device comprises a plurality of vertical channel structures and a plurality of gate layers staked up in a vertical direction. The pluralities of vertical channel structures comprise multiple alternatively stacked source/drain material layers and channel material layers in a vertical direction, and the source/drain material layer comprises p type polysilicon, and the channel material layer comprises n type polysilicon so as to constitute a plurality of junction transistors connected in series vertically, such that not only a smaller component size can be achieved, but also more flexible storage unit operation can be achieved.Type: ApplicationFiled: December 16, 2019Publication date: August 13, 2020Inventors: Deyuan Xiao, Richard R. Chang
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Publication number: 20200075594Abstract: This invention provides a semiconductor device and a manufacturing method thereof.Type: ApplicationFiled: August 29, 2019Publication date: March 5, 2020Inventors: Deyuan Xiao, Richard R. Chang
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Patent number: 10170356Abstract: This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.Type: GrantFiled: June 30, 2016Date of Patent: January 1, 2019Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Patent number: 10100431Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.Type: GrantFiled: September 16, 2016Date of Patent: October 16, 2018Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Publication number: 20180016702Abstract: The present application provides a method for growing monocrystalline silicon by using Czochralski method, comprising: step (1) melting a deuterium-, nitrogen- and barium-doped silicon sheet and a polycrystalline silicon in a crucible; step (2) forming a deuterium- and nitrogen-doped monocrystalline silicon ingot by using magnetic field-applied Czochralski method. The impurity level of the melt and the grown crystal can be reduced according to the present application. By applying rapid thermal annealing to the nitrogen-doped monocrystalline silicon sheet, crystal originated particle defects in surface area of the silicon sheet can be eliminated. The storage of deuterium atoms in gaps of the silicon sheet is able to reduce the contents of oxygen and carbon impurities.Type: ApplicationFiled: December 28, 2016Publication date: January 18, 2018Inventors: DEYUAN XIAO, RICHARD R. CHANG
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Patent number: 9834861Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.Type: GrantFiled: June 30, 2016Date of Patent: December 5, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Patent number: 9837517Abstract: The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.Type: GrantFiled: March 8, 2017Date of Patent: December 5, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Patent number: 9793138Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.Type: GrantFiled: September 16, 2016Date of Patent: October 17, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Patent number: 9779964Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.Type: GrantFiled: June 30, 2016Date of Patent: October 3, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Patent number: 9773670Abstract: A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.Type: GrantFiled: March 11, 2016Date of Patent: September 26, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Publication number: 20170256419Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.Type: ApplicationFiled: June 30, 2016Publication date: September 7, 2017Inventors: DEYUAN XIAO, RICHARD R. CHANG
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Publication number: 20170253993Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.Type: ApplicationFiled: June 30, 2016Publication date: September 7, 2017Inventors: DEYUAN XIAO, RICHARD R. CHANG
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Publication number: 20170256438Abstract: This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.Type: ApplicationFiled: June 30, 2016Publication date: September 7, 2017Inventors: DEYUAN XIAO, RICHARD R. CHANG
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Publication number: 20170256420Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.Type: ApplicationFiled: September 16, 2016Publication date: September 7, 2017Inventors: DEYUAN XIAO, RICHARD R. CHANG
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Publication number: 20170253991Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.Type: ApplicationFiled: September 16, 2016Publication date: September 7, 2017Inventors: DEYUAN XIAO, RICHARD R. CHANG