Abstract: A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

Abstract: The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.

Abstract: The present invention provides a method for forming a quantum well device having high mobility and high breakdown voltage with enhanced performance and reliability. A method for fabrication of a Vertical Cylindrical GaN Quantum Well Power Transistor for high power application is disclosed. Compared with the prior art, the method of forming a quantum well device disclosed in the present invention has the beneficial effects of high mobility and high breakdown voltage with better performance and reliability.

Abstract: A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.

Abstract: A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

Abstract: Present embodiments provide for a CMOS structure and a fabrication method thereof. While the source-drain epitaxial material formed in each of the PMOS device region and the NMOS device region, deuterium gas is used as the carrier gas to store the deuterium atoms in the interstice of the source-drain epitaxial material as an impurity. Since the source-drain epitaxial material is used as a source-drain, which is quite near the gate, the deuterium atoms can diffuse out from the source-drain epitaxial material during the process of forming the gate dielectric layer and covalently bound to the dangling bonds at the interface between the gate dielectric layer and the substrate, so as to obtain more stable structure, avoid penetration of the carriers, and eliminate hot carrier effects, such that performance and resilience of the device are increased.

Abstract: The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.

Abstract: The present invention relates to a method for forming monocrystalline silicon ingot and wafer. When forming a monocrystalline silicon ingot, melted silicon is introduced with a gas comprising deuterium atoms to receive the deuterium atoms at interstice sites, and thus the oxygen, carbon and other impurity contained therein are decreased. When semiconductor devices are formed on wafers, which are formed by the silicon ingot, the deuterium atoms may be diffused out of the silicon wafer to bind to dangling bonds. Then, the structure of the silicon wafer is more stable and resistant to hot carriers, leakage current is lowered, and performance and reliability of the semiconductor devices are promoted.

Abstract: Present embodiments provide for A SOI substrate and fabricating method thereof are provided. The fabricating method of SOI substrate comprises: providing a first substrate, wherein a first dielectric layer is formed on the first substrate; implanting deuterium ions into the first substrate, wherein a deuterium-impurity layer is formed in the first substrate at predetermined depth; providing a second substrate, wherein a second dielectric layer is formed on the second substrate and bounded with the first dielectric layer; performing an annealing process, wherein microbubbles are formed in the deuterium-impurity layer; and cutting the first substrate from the deuterium-impurity layer to obtain the SOI substrate.

Abstract: The present invention relates to a method for forming monocrystalline silicon ingot and wafers. At first, silica is doped with deuterium atoms which is retained in interstices therein. Then, the silica doped with deuterium atoms is utilized for a Czochralski method to form an ingot, which has few oxygen and impurities. The ingot then is utilized to form a wafer. When semiconductor devices are formed on the wafer, the deuterium atoms therein spread out and bind to dangling bonds around the interface to form a relatively stable structure. Therefore, hot carriers may be avoided, leakage may be lowered, and performance and reliability may be promoted.

Abstract: This invention provides a method for forming an epitaxial layer comprising, during formation of the epitaxial layer by vapor phase deposition, introducing a carrier gas containing deuterium. Because of the deuterium atmosphere, the deuterium atoms are introduced in the silicon epitaxial film. During formation of the gate oxide or device, the deuterium atoms are out-diffusion into the interface and covalently bound to the dangling bond to form stable structures. Accordingly, hot carrier effects can be prevented and the properties of the device can be enhanced.

Abstract: The present invention provides a vacuum tube nonvolatile memory and the method of manufacturing it. The vacuum tube nonvolatile memory comprises oxide-nitride-oxide composite structure as gate dielectric layer, wherein the nitride layer can trap charges and provide better insulating block capability between the gate and vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provides with excellent gate controllability and negligible gate leakage current due to adoption of the gate insulator.

Abstract: This invention provides a method for forming a wafer comprising forming a silicon substrate, and then performing rapid thermal annealing to the substrate to form a passivation layer. The passivation layer reduces the surface roughness of the silicon substrate. During the formation of a gate oxide layer or an interface, deuterium can diffuse from the substrate and combine with dangling bonds of the interface to form a stable structure, thereby carrier penetration can be prevented and device properties can be enhanced.

Abstract: A method uses an infrared imaging system to produce an image of a scene. Actual infrared radiation from the scene is detected to form a biased signal representing the radiances of objects wiithin the scene, and the biased signal is diffracted by causing rays of the radiation to pass through an array of lenslets at angles devitated from their normal path. The array includes an infrared transmissive deformable film which retains a pattern stamped into it, the pattern including a plurality of the diffracting lenslets. The diffracted and defocused radiation is detected to form a reference signal, the reference signal is subtracted from the biased signal to obtain an unbiased signal, and an image is generated and displayed in reponse to the unbiased signal.

Abstract: A chopper and method of making same, the chopper being fabricated by initially generating a photomask in conjunction with software. The software provides the lens design to be finally stamped onto the chopper element. A silicon wafer is then etched by reactive ion etching using the photomask to provide the pattern and resulting in a silicon wafer master of the chopper pattern with regions in the shape of lenslets to be formed of desired dimension. The chopper pattern on the silicon wafer is then replicated with a hard material which can be easily stripped from the silicon wafer without damaging either the wafer or the hard material, preferably deposited nickel. The separated nickel replication is then used in conjunction with a heavy press to stamp out sheets of an infrared transmissive flexible film, preferably polyethylene, with the lens pattern in the replication. The film with the lens pattern thereon is the chopper element.

Abstract: A chopper and method of making same, the chopper being fabricated by initially generating a photomask in conjunction with software. The software provides the lens design to be finally stamped onto the chopper element. A silicon wafer is then etched by reactive ion etching using the photomask to provide the pattern and resulting in a silicon wafer master of the chopper pattern with regions in the shape oflenslets to be formed of desired dimension. The chopper pattern on the silicon wafer is then replicated with a hard material which can be easily stripped from the silicon wafer without damaging either the wafer or the hard material, preferably deposited nickel. The separated nickel replication is then used in conjunction with a heavy press to stamp out sheets of an infrared transmissive flexible film, preferably polyethylene, with the lens pattern in the replication The film with the lens pattern thereon is the chopper element. The system is designed to operate in the 8 to 13.5 micron range.

Abstract: Pharmacuetical compositions for administering a combination of controlled release potassium chloride and immediately-released magnesium salt are disclosed.

Abstract: A module containing an integrated circuit, such as a read-only memory (ROM), includes an essentially box-shaped plastic housing having an internal chamber in which the integrated circuit is located. Positioned within the chamber is a printed circuit board on which the integrated circuit is mounted. Also mounted on the printed circuit board and adjacent to an elongated narrow slot located in one side of the housing are a plurality of electrical spring contacts electrically connected to the integrated circuit by means of electrical conductors on the printed circuit board. Upon insertion of the module into an electronic apparatus, edge connectors of a printed circuit board of the electronic apparatus extend through the narrow slot and engage the electrical spring contacts, thereby electrically connecting the integrated circuit to the apparatus.