Abstract: An apparatus (2) comprises an instruction decoder (6) and processing circuitry (4). The instruction decoder (6) supports branch instructions for triggering a non-sequential change of program flow to an instruction at a target address, including: a branch-with-link instruction for which a return address is set for a subsequent return of program flow; and at least one target-checking type of branch instruction, for which when the branch is taken an error handling response is triggered when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction. For at least a subset of the at least one target-checking type of branch instruction, a branch target variant of the branch-with-link instruction is a permitted type of branch target instruction.

Abstract: Methods of additively printing an extension segment on a workpiece may include pretreating a workpiece-interface of a workpiece using an energy beam from an additive manufacturing machine, providing a pretreated workpiece-interface having received a pretreatment, with the pretreatment remediating an aberrant feature of the workpiece and/or the workpiece-interface. Such methods may additionally include additively printing an extension segment on the pretreated workpiece-interface using the energy beam from the additive manufacturing machine. Exemplary additive manufacturing system for printing an extension segment on a workpiece may include a controller operably coupled to a vision system and an additive manufacturing machine.

Abstract: A tooling assembly and method of aligning a plurality of components for a repair process in an additive manufacturing machine includes positioning the plurality of components such that a repair surface of each of the plurality of components contacts an alignment plate, e.g., under the force of gravity or using biasing members. The method further includes surrounding the alignment plate with containment walls to define a reservoir around the plurality of components and dispensing a fill material, such as wax or a potting material, into the reservoir which is configured for fixing a relative position of the plurality of components when the fill material is solidified.

Abstract: A system (50) and method (200) for repairing one or more components (70) using an additive manufacturing process includes securing the components (70) in a tooling assembly (52) such that a repair surface (72) of each component (70) is positioned within a single build plane (82), determining a repair toolpath (76) corresponding to the repair surface (72) of each component using a vision system (56), depositing a layer of additive powder (72) over the repair surface (72) of each component (70) using a powder dispensing assembly (112), and selectively irradiating the layer of additive powder (72) along the repair toolpath (76) to fuse the layer of additive powder (72) onto the repair surface (72) of each component (70).

Abstract: An additive manufacturing system may include a controller operably coupled to a vision system and an additive manufacturing machine. The controller may be configured to determine a workpiece-interface of each of a plurality of workpieces from one or more digital representations of one or more fields of view having been captured by a vision system and determining one or more coordinates of the workpiece-interface of respective ones of the plurality of workpieces, and to transmit one or more print commands to an additive manufacturing machine so as to additively print a plurality of extension segments on the workpiece-interface of respective ones of the plurality of workpieces, with the one or more print commands having been generated based at least in part on the one or more digital representations of the one or more fields of view.

Abstract: Provided are workpiece-assemblies, and systems and methods for aligning a plurality of workpieces with a build plane. A system may include an alignment plate, one or more elevating blocks, and a workpiece-assembly. A workpiece-assembly may include a build plate that has a plurality of workpiece docks, a plurality of workpiece shoes that have a slot configured to receive a portion of one or more workpieces respectively inserted or insertable into the plurality of workpiece docks, a plurality of biasing members respectively situated or situatable between the build plate and the plurality of workpiece shoes so as to exert a biasing force upon the workpiece shoes, and one or more clamping mechanisms coupled or couplable to the build plate and operable to secure the plurality of workpiece shoes within the respective workpiece docks.

Abstract: An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions, and memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. The memory access circuitry determines, according to a programmable mapping, a mapping of guard tag storage locations for storing guard tags for corresponding blocks of memory locations.

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks.

Abstract: An additive manufacturing system may include a controller operably coupled to a vision system and an additive manufacturing machine. The controller may be configured to determine in a library-CAD model, a nominal model-interface traversing a nominal model corresponding to a workpiece, to compare the nominal model-interface of the library-CAD model to a digital representation of a workpiece-interface of the workpiece, where the digital representation has been obtained using the vision system, and to generate a model of an extension segment based at least in part on the nominal model-interface, with the model of the extension segment being configured to be additively printed on the workpiece-interface of the workpiece.

Abstract: In an apparatus with transactional memory support circuitry, for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.

Abstract: An electrical regeneration and vehicle deceleration control method comprises operating an electrified powertrain in normal or maximum regeneration modes associated with lesser and greater electrical regeneration and vehicle deceleration rates, respectively, receiving an input from a driver of the vehicle indicative of a request to enable the maximum regeneration mode, detecting a status indicative of an availability of the maximum regeneration mode, and in response to receiving the request and based on the status of the maximum regeneration mode and a current vehicle deceleration rate: (i) operating the electrified powertrain in either the maximum regeneration mode or a normal regeneration mode, (ii) selectively outputting a message to the driver indicative of the status of the maximum regeneration mode, and (iii) selectively commanding a hydraulic brake system of the vehicle to generate brake force based on a driver-expected vehicle deceleration rate associated with the operative regeneration mode.

Abstract: An apparatus comprising memory access circuitry to perform a tag-guarded memory access in response to a received target address and methods of operation of the same are disclosed. In the tag-guarded memory access a guard-tag retrieval operation seeks to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address, and a guard-tag check operation compares an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation. When the guard-tag retrieval operation is unsuccessful in retrieving the guard tag, a substitute guard tag value is stored as the guard tag in association with the block of one or more memory locations comprising the addressed location identified by the target address.

Abstract: An apparatus comprises: an instruction decoder and processing circuitry. In response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder controls the processing circuitry to perform a processing operation on at least one input data structure to generate an output data structure. Each input/output data structure comprises an arrangement of data corresponding to a plurality of memory addresses. The apparatus comprises two or more sets of one or more data structure metadata registers, each set associated with a corresponding data structure identifier and designated to store address-indicating metadata for identifying the memory addresses for the data structure identified by the corresponding data structure identifier.

Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus includes storage to store bounded pointers, where each bounded pointer comprises a pointer value and associated attributes, with the associated attributes including range information indicative of an allowable range of addresses when using the pointer value. Processing circuitry is used to perform a signing operation on an input bounded pointer in order to generate an output bounded pointer in which a signature generated by the signing operation is contained within the output bounded pointer in place of specified bits of the input bounded pointer. In addition, the associated attributes include signing information which is set by the processing circuitry within the output bounded pointer to identify that the output bounded pointer has been signed. Such an approach provides increase resilience to control flow integrity attack when using bounded pointers.

Abstract: A projectile (100) with incidence steerable control surfaces (2) each pivotable with respect to the projectile (100), comprises: central control means (5) for controlling the control surfaces (2), a control arm (11) adapted to rotate the central control means (5) around pitch (Y) and yaw (Z) axes of the projectile (100), positioning means for positioning the arm (11), adapted to position one end of the arm (11) in a position determined with respect to an absolute reference frame, the positioning means comprising a cone (13) movable in translation so as to pivot the central control means around an orientation axis (AO), and a toothed wheel (16) meshing with a motorization intended to pilot the angular position of the orientation axis in an absolute reference frame.

Abstract: An apparatus (2) comprises an instruction decoder (6) and processing circuitry (4). The instruction decoder (6) supports branch instructions for triggering a non-sequential change of program flow to an instruction at a target address, including: a branch-with-link instruction for which a return address is set for a subsequent return of program flow; and at least one target-checking type of branch instruction, for which when the branch is taken an error handling response is triggered when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction. For at least a subset of the at least one target-checking type of branch instruction, a branch target variant of the branch-with-link instruction is a permitted type of branch target instruction.

Abstract: A system and method are presented in which a flow of plastic is extruded to obtain nano-sized features by forming multiple laminated flow streams, flowing in parallel through the non-rotating extrusion system. Each of the parallel laminated flow streams are subjected to repeated steps in which the flows are compressed, divided, and overlapped to amplify the number of laminations. The parallel amplified laminated flows are rejoined to form a combined laminated output with nano-sized features. The die exit is formed to provide a tubular shape.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.