Abstract: A heat transfer system comprises a substrate and a thin film coating in physical and thermal contact with the substrate at an interface. The substrate is configured to transmit thermal waves, and has a first effusivity and a first thickness.

Abstract: Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract: A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered.

Abstract: A method is disclosed for clearing effusion from an ear. The method may include applying liquid to an ear canal, which is proximal to a perforated tympanic membrane, which is proximal to a middle ear containing effusion, applying an ear device to seal and pressurize the liquid inside the ear canal, the ear device regulating the amount of pressure inside the ear canal, and inducing a Eustachian tube, which is distal to the middle ear, to open, which causes the fluid to displace the effusion into the Eustachian tube.

Abstract: An electrical energy generating system in which high pressure slurry is used to expel water, alternately from two bladders, which is used to power a turbine which drives a generator.

Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract: Methods, systems, and devices for dynamically aggregating content, especially digital content, are described. These include tools and techniques for automatically creating a unique package that tells a user-specific story about memorable life events. Electronic media files such as photographs, videos, and the like, of a user may be captured and linked to a unique identifier. The electronic media files may be transmitted to a central server where they may be aggregated and utilized to generate a multimedia file for user. The multimedia file may include electronic media files captured at disparate locations and times, and it may include stock content, user-generated content, third-party content, and the like. Users may access archived stories (e.g., multimedia files) in a virtual bookshelf Third-parties may be compensated for their content that is provided to a user.

Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract: A data processing system 2 supporting multiple modes of operation is provided with illegal change detecting circuitry 22 which detects attempts by program instructions to perform an illegal change of mode, such as a change to a higher level of privilege in response to execution of a mode changing program instruction or an exception return instruction. If such a change is detected, then an illegal change bit CPSR.IL is set. An instruction decoder 12 is responsive to the illegal change bit having a set value to treat subsequent program instructions as undefined instructions. These undefined instructions may then trigger an undefined instruction exception or other type of response.

Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.

Abstract: A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.

Abstract: Page table data for each page within a memory address space includes a write permission flag and a dirty-bit-modifier flag. The write permission flag is initialised to a value indicating that write access is not permitted. When a write access occurs, then the dirty-bit-modifier flag indicates whether or not the action of the write permission flag may be overridden. If the action of the write permission flag may be overridden, then the write access is permitted and the write permission flag is changed to indicate that write access is thereafter permitted. A page for which the write permission flag indicates that writes are permitted is a dirty page.

Abstract: A valve with a housing (12) in which is formed a chamber (14), an inlet (16) to the chamber, an outlet (18) from the chamber which is at a right angle relative to the inlet, a metallic valve seat (90) at the inlet, a resilient valve seal (100) mounted to the valve seat at the inlet and a spherical valve member (40) inside the chamber.

Abstract: An aircraft ice protection system includes a heating substrate with a coating in intimate thermal contact with the heating substrate. The thermal effusivities of the heating substrate and the coating are different from one another for interference of thermal waves reflected from the coating with thermal waves generated in the heating substrate. A pulse generator can be operatively connected to the heating substrate to convert pulsed electrical power from the pulse generator into thermal energy for ice removal or prevention.

Abstract: An arrow-type sub-caliber projectile has a piercing bar which is cylindrical about a longitudinal axis, extended by a conical portion, and is surrounded by a sabot made of a lightweight material and allows the firing of the projectile in a weapon. This conical portion has a tip of a heating-resistant material with a maximum diameter less than half the diameter of the bar, the tip being connected to the bar by a support structure having no ballistic effects, the bar having a flat front face which is perpendicular to the longitudinal axis of the bar, the flat front face area being substantially equal to the cross-sectional area of the bar, thus with no element with ballistic effects interposed between the flat front face of the bar and the tip.

Abstract: A data processing apparatus is provided comprising processing circuitry and instruction decoding circuitry. The data processing apparatus is capable of operating at a plurality of different privilege. Processing circuitry of the data processing apparatus imposes on program instructions different access permissions to at least one of a memory and a set of registers at different ones of the different privilege levels. A debug privilege-level switching instruction is provided and decoding circuitry is responsive to this instruction to switch the processing circuitry from a current privilege level to a target privilege level if the processing circuitry is in a debug mode. However, if the processing circuitry is in a non-debug mode the instruction decoding circuitry prevents execution of the privilege-level switching instruction regardless of the current privilege level.

Abstract: A hard drive carrier includes a substrate and an elastomer pad. The substrate includes a pin and an opening. The opening has a perimeter, and the pin is dimensioned to fit inside of a mounting hole of a hard drive. The elastomer pad is molded over or around the pin, or may be place anywhere convenient for dampening vibration in the direction of the pin axis. The elastomer pad spans the opening. The elastomer is attached to the perimeter of the opening, and the elastomer pad has a protruding feature within the perimeter of the opening.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.