Abstract: A processor may include a plurality of data memories storing operands that may be operated upon by the processor. Load/store operations may specify a memory location in one of the data memories to be accessed using a memory select value that selects the data memory and an address within the selected data memory. The memory select values may be mapped from virtual memory select values associated with the load/store operations to physical memory select values that may be used to access the data memory.

Abstract: A hardware scheduling circuit may receive priority indications for a plurality of threads for processing, by an execution unit, multiple data samples associated with a signal. A particular thread of the plurality of threads may be scheduled for execution by the execution unit based on a priority of the particular thread and based on an availability of some of the multiple data samples that are to be processed by the particular thread.

Abstract: In various embodiments, a floating-point arithmetic circuit includes a range exception detection circuit and an output circuit. The range exception detection circuit may generate a selection signal that indicates whether a floating-point arithmetic result generated within the floating-point arithmetic circuit is within a specified range. The output circuit may output the floating-point arithmetic result in response to the selection signal indicating the floating-point arithmetic result is within a specified range. The output circuit may output a corresponding specified value in response to the selection signal indicating the floating-point arithmetic result is not within the specified range. Accordingly, floating-point arithmetic operations may be performed in combination with an operation that limits a range of an output to a specified range.

Abstract: A hardware scheduling circuit may receive priority indications for a plurality of threads for processing, by an execution unit, multiple data samples associated with a signal. A particular thread of the plurality of threads may be scheduled for execution by the execution unit based on a priority of the particular thread and based on an availability of some of the multiple data samples that are to be processed by the particular thread.

Abstract: A method and apparatus for implementing FIR filters in a processor includes a plurality of execution units executing instructions of an instruction set. The execution units include a number of FIR filter circuits, each of which is associated with a corresponding one of a number FIR filter instructions. Furthermore, each of the FIR filter circuits is and dedicated exclusively to executing its corresponding one of the FIR filter instructions. Each FIR filter execution unit receives input data and provides filtered output data.

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract: In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

Abstract: An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard. sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register.

Abstract: A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: An apparatus for generating control signals of a microprocessor includes a memory, for example, a pattern holding register storing an arbitrary bit pattern. The holding register can be loaded by software. A shift register is connected to receive the bit pattern from the pattern register. An output pin of the microprocessor receives each bit of the arbitrary bit pattern, directly, or indirectly via a bus interface unit, at a rate determined by a clock signal to generate control signals for arbitrary external devices.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first instruction set and the second program code is executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set.A first computer translates the first code instructions to corresponding second code instructions in accordance with a pattern code that defines first code instructions in terms of second code instructions.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.