Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: An instruction eases exception handling in a data processing system having one or more parallel pipelined execution units by permitting the central processing unit to complete instructions currently being processed by the execution units, but preventing further instructions from being initiated until all currently executing instructions have been completed and all outstanding exception conditions have been resolved. After all the instructions preceding the DRAIN instruction of the present invention in the program instruction sequence have been executed, the central processing unit can continue to execute the sequential program instructions when no arithmetic exception has been identified, or can invoke an exception handling procedure when an arithmetic exception has been identified. The instruction is typically positioned in an instruction sequence after an instruction that has high degree of probability of resulting in the identification of an arithmetic exception condition.

Abstract: A central processing unit (CPU) executing a virtual memory management system employs a translation buffer for caching recently used page table entries. When more than one process is executing on the CPU, the translation buffer is usually flushed when a context switch is made, even though some of the entries would still be valid for commonly-referenced memory areas. An address space number feature is employed to allow entries to remain in the translation buffer for processes not currently executing, and the separate processes or the operating system can reuse entries in the translation buffer for such pages of memory that are commonly referenced. To allow this, an "address space match" entry in the page table entry signals that the translation buffer content can be used when the address tag matches, even though the address space numbers do not necessarily match.

Abstract: In a data processing system, apparatus and method for controlling the type of processing to which data signal groups can be subjected includes a page table entry format having a multiplicity of field positions for storing signals defining page access rights. In addition to the read/write access control, the signal group access rights can be determined by the current mode of operation of the data processing unit and the intended activity of the addressed instruction or data element (i.e., read, write or execute).

Abstract: In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto.

Abstract: In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register.

Abstract: In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the execution of a macroinstruction is atomic (i.e., executed as a single entity). Data processing systems that do not employ microcode typically have simpler macroinstruction sets that do not provide for a similar atomicity for complex instruction sequences.

Abstract: A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Abstract: In a data procesing system having a kernel mode (i.e., for executing privileged instructions) and a user mode of operation, apparatus for responding to interrupt conditions includes a first register, subject to the control of the currently executing program for enabling the generation of a mode-related interrupt signal and includes a second register for indicating the presence of a pending mode-related interrupt condition and a third register for requesting a mode-related interrupt be entered in the second register. The mode of operation and the enable and pending interrupt condition registers are monitored and when the signals in the two registers have the appropriate relationship, an interrupt signal is generated to which a control program will respond. The contents of the first register can be controlled by the currently executing program which can control the enabling signal for the currently executing mode.

Abstract: In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.

Abstract: A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also determined whether a data block requested in the instruction by one of the processors is located in a corresponding cache, and if so, the requested data block is returned to the processor. If the data block is not in the cache and the write-intent flag indicates that the block will not be modified, the data block is read from main memory without obtaining a write privilege. The requested data block is subsequently returned from the cache to the processor. If the data block is not in the cache and the write-intent flag indicates the data block will be modified by the processor, then the data block is read from main memory while obtaining the write privilege. Subsequently, the requested data block is returned from the cache to the processor.

Abstract: In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g, the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register.