Patents by Inventor Richard Te GAN
Richard Te GAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967507Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: GrantFiled: December 6, 2021Date of Patent: April 23, 2024Assignee: NXP USA, INC.Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
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Publication number: 20230369248Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Scott M. Hayes, Michael B. Vincent, Zhiwei Gong, Richard Te Gan, Vivek Gupta
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Patent number: 11791283Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.Type: GrantFiled: April 14, 2021Date of Patent: October 17, 2023Assignee: NXP USA, INC.Inventors: Scott M. Hayes, Michael B. Vincent, Zhiwei Gong, Richard Te Gan, Vivek Gupta
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Patent number: 11728285Abstract: A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.Type: GrantFiled: August 26, 2021Date of Patent: August 15, 2023Assignee: NXP USA, INC.Inventors: Vivek Gupta, Michael B. Vincent, Scott M. Hayes, Richard Te Gan, Zhiwei Gong
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Patent number: 11705410Abstract: A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.Type: GrantFiled: December 11, 2020Date of Patent: July 18, 2023Assignee: NXP USA, INC.Inventors: Michael B. Vincent, Vivek Gupta, Richard Te Gan, Kabir Mirpuri
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Publication number: 20230066652Abstract: A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Vivek Gupta, Michael B. Vincent, Scott M. Hayes, Richard Te Gan, Zhiwei Gong
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Publication number: 20220392777Abstract: A method of manufacturing a packaged semiconductor device is provided. The method includes placing a plurality of semiconductor die on a carrier substrate. The plurality of semiconductor die and an exposed portion of the carrier substrate are encapsulated with an encapsulant. A cooling fixture includes a plurality of nozzles and is placed over the encapsulant. The encapsulant is cooled by way of air exiting the plurality of nozzles. A property of air exiting a first nozzle of the plurality of nozzles is different from that of a second nozzle of the plurality of nozzles.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Inventors: Zhiwei Gong, Scott M. Hayes, Michael B. Vincent, Vivek Gupta, Richard Te Gan
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Publication number: 20220336371Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.Type: ApplicationFiled: April 14, 2021Publication date: October 20, 2022Inventors: Scott M. Hayes, Michael B. Vincent, Zhiwei Gong, Richard Te Gan, Vivek Gupta
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Patent number: 11404288Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel by placing a plurality of semiconductor die on a major side of a carrier substrate and encapsulating with an encapsulant the plurality semiconductor die and the major side of the carrier substrate. A plurality of warpage control features are formed with the encapsulant while encapsulating. The method further includes placing the panel onto a warpage control fixture to substantially flatten the panel. The plurality of warpage control features interlock with mating features of the warpage control fixture.Type: GrantFiled: March 23, 2021Date of Patent: August 2, 2022Assignee: NXP USA, INC.Inventors: Michael B. Vincent, Scott M. Hayes, Zhiwei Gong, Vivek Gupta, Richard Te Gan
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Publication number: 20220189890Abstract: A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Inventors: Michael B. Vincent, Vivek Gupta, Richard Te Gan, Kabir Mirpuri
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Publication number: 20220093416Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
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Patent number: 11222790Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: GrantFiled: April 29, 2020Date of Patent: January 11, 2022Assignee: NXP USA, INC.Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
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Publication number: 20210202267Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: ApplicationFiled: April 29, 2020Publication date: July 1, 2021Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
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Patent number: 10192837Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.Type: GrantFiled: December 20, 2017Date of Patent: January 29, 2019Assignee: NXP B.V.Inventors: Chung Hsiung Ho, Wayne Hsiao, Richard Te Gan, James Raymond Spehar
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Patent number: 9881863Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: February 8, 2017Date of Patent: January 30, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Publication number: 20170148722Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio B. DIMAANO, JR., Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
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Patent number: 9589875Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: September 9, 2015Date of Patent: March 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Publication number: 20150380346Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
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Patent number: 9136142Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: April 21, 2014Date of Patent: September 15, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Publication number: 20140227832Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: United Test and Assembly Center Ltd.Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG