Patents by Inventor Richard Te GAN

Richard Te GAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor packages and methods of packaging semiconductor devices
    Patent number: 8716873
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: May 6, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
    Publication number: 20120001306
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 5, 2012
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
  • SHRINK PACKAGE ON BOARD
    Publication number: 20100102436
    Abstract: A method of forming a device is disclosed. The method includes providing a printed circuit board substrate having a die attach region on a first surface of the substrate. The method also includes attaching a die to a die attach region. The die is electrically coupled to first land pads disposed on the first surface at the periphery of the die attach region. A cap is formed in a target area by a top gate process to produce a cap with an even surface. The cap covers the die and leaves at least the first land pads exposed.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 29, 2010
    Applicant: United Test and Assembly Center Ltd.
    Inventors: Kian Teng ENG, Rodel MANALAC, Teck Wah PARK, Richard Te GAN