Patents by Inventor Richard W. Citta

Richard W. Citta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7519088
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: April 14, 2009
    Assignee: Zenith Electronics LLC
    Inventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
  • Publication number: 20090080537
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 26, 2009
    Inventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
  • Patent number: 7504890
    Abstract: A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: March 17, 2009
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia, Wenjun Zhang
  • Publication number: 20090024897
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Application
    Filed: October 31, 2007
    Publication date: January 22, 2009
    Applicant: Zenith Electronics Corporation
    Inventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
  • Publication number: 20080260014
    Abstract: A method of synchronizing a feedforward filter (46) that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols (60), wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method further includes the steps of estimating a channel impulse response from the plurality of samples, calculating a characteristic of the channel impulse response, and synchronizing (54) the feedforward filter in accordance with the estimated channel impulse response.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 23, 2008
    Inventors: Xiaojun Yang, Richard W. Citta, Scott M. Lopresto
  • Patent number: 7418034
    Abstract: An adaptive equalizer comprises a trellis decoder; a mapper coupled to the output of the trellis decoder; and a decision feedback equalizer coupled to the output of the mapper. Each of the taps receives as input via the mapper output from a different one of the stages of the trellis decoder.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: August 26, 2008
    Assignee: Micronas Semiconductors. Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang
  • Publication number: 20080107168
    Abstract: A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.
    Type: Application
    Filed: April 8, 2005
    Publication date: May 8, 2008
    Applicant: MICRONAS SEMICONDUCTORS, INC.
    Inventors: Jingsong Xia, Shidong Chen, Richard W. Citta, Gopalan Krishnamurthy, Scott M. Lopresto, David A. Willming, Xiaojun Yang, Jilian Zhu
  • Publication number: 20080063043
    Abstract: An equalizer (200A) comprises a feedforward filter (210), wherein the feedforward filter includes a plurality of feedforward filter taps, coefficients are associated with the plurality of feedforward filter taps, and values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined. In some embodiments, the equalizer also comprises a decision feedback equalizer (216).
    Type: Application
    Filed: April 8, 2005
    Publication date: March 13, 2008
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. Lopresto
  • Publication number: 20080049824
    Abstract: A method of synchronizing a feedforward filter that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols, wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method further includes the steps of estimating a channel impulse response from the plurality of samples, wherein the channel impulse response estimate is represented by a plurality of correlation values, identifying a maximum correlation value from the plurality of correlation values, defining a window relative to the maximum correlation value, calculating a characteristic of the correlation values within the window, and synchronizing the feedforward filter in accordance with the characteristic.
    Type: Application
    Filed: April 8, 2005
    Publication date: February 28, 2008
    Inventors: Xiaojun Yang, Richard W. Citta, Scott M. Lopresto
  • Publication number: 20080049871
    Abstract: A method of controlling sampling frequency of a sampling device (40), where the sampling device (40) generates samples (62) in response to the receipt of a signal (20) resulting from a transmission of a series of symbols through a channel, the method including the steps of estimating (46) a channel impulse response of the channel from the samples, calculating a characteristic of the channel impulse response estimate, and determining (52) the sampling frequency in accordance with the characteristic.
    Type: Application
    Filed: April 8, 2005
    Publication date: February 28, 2008
    Inventors: Xiaojun Yang, Richard W. Citta, Scott M. Lopresto
  • Patent number: 7305026
    Abstract: An equalizer for processing blocks of data includes n?1 data shifters, n finite filters, an adder, and a controller. Each of the n?1 data shifters shifts the blocks of data. One of the n finite filters applies a corresponding set of finite filter coefficients to the blocks of data, and each of the other n?1 finite filters applies a set of finite filter coefficients to a corresponding output of the n?1 data shifters. Ghosts of the blocks of data are not eliminated as a result of the application of the n sets of finite filter coefficients corresponding to the n finite filters, and n>2. The adder is arranged to add outputs from the n finite filters. The controller is arranged to control the sets of finite filter coefficients corresponding to the n finite filters so that the addition performed by the adder substantially eliminates the ghosts.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: December 4, 2007
    Assignee: Zenith Electronics Corporation
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia
  • Patent number: 7272203
    Abstract: A data-and-pilot directed frequency-and-phase lock loop for an offset-QAM modulated signal having a pilot signal comprising a pilot acquisition loop and a pair of data-directed acquisition loops. The pilot is extracted from the main signal by a pilot filter, then used both by the pilot acquisition loop and to remove the pilot from the signal to the data-directed acquisition loops. The outputs of the pilot and the two data-directed acquisition loops are summed and returned to the VCO to complete the feedback loop.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: September 18, 2007
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia, Wenjun Zhang
  • Patent number: 7215714
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 8, 2007
    Assignee: Zenith Electronics Corporation
    Inventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
  • Patent number: 7190744
    Abstract: An equalizer comprises: an FIR; a trellis decoder coupled to the FIR; a mapper coupled to the trellis decoder; and a decision feedback equalizer coupled to the mapper. The decision feedback equalizer receives the mapped and scaled output of the trellis decoder as input and an error signal is generated by subtracting an output of the decision feedback equalizer from the input to the trellis decoder.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: March 13, 2007
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang
  • Patent number: 7187698
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: March 6, 2007
    Assignee: Zenith Electronics Corporation
    Inventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
  • Patent number: 7177343
    Abstract: A compound chirp is provided in a received signal to permit a receiver to synchronize to the received signal. The compound chirp has temporally overlapping up frequency and down frequency components.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: February 13, 2007
    Assignee: Zenith Electronics Corporation
    Inventors: Richard W. Citta, Jingsong Xia
  • Patent number: 7130344
    Abstract: An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: October 31, 2006
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang, Hangbin Song
  • Patent number: 7072392
    Abstract: A digital equalizer comprises a matched filter that, in conjunction with an FIR filter, assures a single peak with substantially greater energy than other peaks caused by ghosts, thereby permitting synchronization even with multiple, arbitrarily strong ghosts caused by strong multipathing, multiple transmitters, or both.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: July 4, 2006
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang
  • Patent number: 6996133
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data, The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: February 7, 2006
    Assignee: Zenith Electronics Corporation
    Inventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
  • Patent number: 6995617
    Abstract: A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: February 7, 2006
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia, Wenjun Zhang