Abstract: A data-directed frequency-acquisition loop capable of generating a frequency error having a magnitude and direction from a double sideband suppressed signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is convolved by a second multiplier. The I output of the second multiplier passes through a first low-pass filter. The filtered I output and the Q output are then multiplied by a third multiplier. The output of the third multiplier is filtered through a second low-pass filter, amplified, and return to the VCO to complete the feedback loop.

Abstract: In an enhanced slice prediction embodiment, an input containing first and second data is received. Each data element of the first data represents a number of bits that is greater than a number of bits represented by each data element of the second data, and the first and second data in the received input are defined by the same n level constellation. The input is decoded with a first decoder to recover both the first and second data. Only the second data is decoded with a second decoder. Enhanced slice prediction is provided based on the decoding of the second decoder.

Abstract: A receiver includes an equalizer and a decoder which decodes data from a signal. The signal is based upon an output of the equalizer. The receiver also includes an encoder, which re-encodes the decoded data, and an error generator, which generates an error vector based upon the signal and the encoded data and which weights the error vector according to a reliability that the decoder accurately decoded the data from the signal. A controller controls the equalizer in response to the weighted error vector.

Abstract: An equalizer substantially eliminates a ghost of a received main signal by (i) applying coefficients b (where b may be equal to one) to the received main signal and the ghost in order to modulate the received main signal and the ghost so that the received main signal and the ghost are unequal, (ii) applying coefficients a to the modulated received main signal and ghost in order to substantially eliminate the ghost, and (iii) applying coefficients c as a window function to the substantially ghost-free received main signal in order to remove the modulation imposed on the received main signal by the coefficients b.

Abstract: An equalizer includes n processing paths arranged to process blocks of data. N?1 data shifters are arranged so that each of the n?1 data shifters is in a corresponding one of the n processing paths and so that one of the n processing path has no data shifter. N finite filters are arranged so that each of the n finite filters is in a corresponding one of the n processing paths, and so that each of the n finite filters applies a corresponding set of finite filter coefficients to the blocks of data. Ghosts of the blocks of data are not eliminated as a result of the application of the sets of finite filter coefficients corresponding to the n finite filters, and n>2. An adder is arranged to add outputs from the n processing paths such that the addition eliminates ghosts of the blocks of data.

Abstract: An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.

Abstract: A receiver includes an equalizer and a decoder which decodes data from a signal. The signal is based upon an output of the equalizer. The receiver also includes an encoder, which re-encodes the decoded data, and an error generator, which generates an error vector based upon the signal and the encoded data and which weights the error vector according to a reliability that the decoder accurately decoded the data from the signal. A controller controls the equalizer in response to the weighted error vector.

Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

Abstract: An equalizer that processes blocks of data includes a first finite filter which applies first finite filter coefficients to the blocks of data and a first post-processor which applies first post-processor coefficients to an output of the first finite filter. Ghosts of the blocks of data are not eliminated as a result of the application of the first finite filter coefficients and the first post-processor coefficients. The equalizer also includes a second finite filter which applies second finite filter coefficients to the blocks of data, and a second post-processor which applies second post-processor coefficients to an output of the second finite filter. Ghosts of the blocks of data are not eliminated as a result of the application of the second finite filter coefficients and the second post-processor coefficients. However, an adder adds outputs from the first and second post-processors so that ghosts of the blocks of data are eliminated from an output of the adder.

Abstract: An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.

Abstract: An equalizer applies a window function to input blocks of data. A first finite filter multiplies each of the windowed input blocks of data with a first set of finite filter coefficients to provide respective first adjusted output blocks of data. This multiplication does not result in a full solution to ghosts. A second finite filter multiplies each of the windowed input blocks of data with a second set of finite filter coefficients to provide respective second adjusted output blocks of data. This multiplication also does not result in a full solution to ghosts. An adder performs an addition based upon corresponding ones of the first and second adjusted output blocks of data. A controller controls the window function and the first and second sets of equalizer coefficients so that, as a result of the addition, a substantially full solution to ghosts is obtained.

Abstract: An iterative decoding system has a first decoder that decodes coded data and a first weighting circuit that reduces channel effects in the coded data based upon a reliability that the first decoder accurately decoded the encoded data. The first weighting circuit produces improved coded data. A second decoder of the iterative decoding system decodes the improved coded data, and a second weighting circuit additionally reduces channel effects in the improved coded data based upon a reliability that the second decoder accurately decoded the improved encoded data.

Abstract: An equalizer substantially eliminates a ghost of a received main signal by (i) applying coefficients b (where b may be equal to one) to the received main signal and the ghost in order to modulate the received main signal and the ghost so that the received main signal and the ghost are unequal, (ii) applying coefficients a to the modulated received main signal and ghost in order to substantially eliminate the ghost, and (iii) applying coefficients c as a window function to the substantially ghost-free received main signal in order to remove the modulation imposed on the received main signal by the coefficients b.

Abstract: An equalizer substantially eliminates a ghost of a received main signal by (i) applying coefficients b (where b may be equal to one) to the received main signal and the ghost in order to modulate the received main signal and the ghost so that the received main signal and the ghost are unequal, (ii) applying coefficients a to the modulated received main signal and ghost in order to substantially eliminate the ghost, and (iii) applying coefficients c as a window function to the substantially ghost-free received main signal in order to remove the modulation imposed on the received main signal by the coefficients b.

Abstract: A transmitter transmits, and a receiver receives, a data frame is transmitted into an 8 MHZ channel. The data frame contains a plurality of data segments, where each of the data segments contain DS symbols. The DS symbols include data symbols, priming symbols, and segment synchronization symbols. The transmitter trellis encodes the data symbols, priming symbols, and segment synchronization symbols. The receiver trellis decodes the data symbols, priming symbols, and segment synchronization symbols. The data frame also contains a mode control ID which the receiver uses in trellis decoding the data symbols, priming symbols, and segment synchronization symbols.

Abstract: A system and method for symbol clock recovery independent of segment location recovery uses the frequency and phase information in the upper and lower band edges of a signal to generate a signal for correcting the symbol clock. A particular combination of raised-root cosine filters, low-pass filters, multipliers, and adders effectively uses the tails of a received signal in the frequency domain to correct phase errors.

Abstract: A data-directed frequency-acquisition loop capable of generating a frequency error having a magnitude and direction from a double sideband suppressed signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is convolved by a second multiplier. The I output of the second multiplier passes through a first low-pass filter. The filtered I output and the Q output are then multiplied by a third multiplier. The output of the third multiplier is filtered through a second low-pass filter, amplified, and return to the VCO to complete the feedback loop.

Abstract: A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.

Abstract: A dual path equalizer for processing blocks of data includes first and second pre-processors, first and second finite filters, first and second post-processors, and an adder. The first pre-processor applies coefficients b1 to a received signal, the first finite filter applies coefficients a1 to an output of the first pre-processor in order to substantially eliminate a ghost from the received signal, and the first post-processor applies coefficients c1 to an output of the first finite filter. The second pre-processor applies coefficients b2 to the received signal, the second finite filter applies coefficients a2 to an output of the second pre-processor in order to substantially eliminate a ghost from the received signal, and the second post-processor applies coefficients c2 to an output of the second finite filter.

Abstract: Circuits for removing clock related artifacts in an offset QAM generated VSB signal includes a transmitter arrangement and a receiver arrangement. In the transmitter, a detector detects the artifacts and a correlator determines whether the artifacts repeat over two symbols or over four symbols. A signal indicative of the artifacts is used to control processing circuits for adjusting the ratios and levels of the I and Q signal components of the QAM signal for substantially eliminating the artifacts. In the receiver, the received VSB signal is divided into four parallel signals. Each parallel signal is processed to develop an average symbol level that is subtracted before the parallel signals are recombined. The four symbol repeat rate artifacts reflect a DC offset of the VSB signal symbols, which are both positive-going and negative-going and which therefore average to zero for random signals. Averaging is done over N symbols where N is a power of 2.