Patents by Inventor Richard Westhoff

Richard Westhoff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190226340
    Abstract: A gasket for concrete structures such as tunnel segments includes a gasket body having a bottom face configured to be positioned against a surface of an associated tunnel segment. First and second anchor members protrude from opposed side edges of the gasket adjacent the bottom face of the gasket. The anchor members are configured to attach the gasket to the tunnel segment during casting of a precast concrete member. The gasket body forms a groove in the concrete member and the anchor members form side channels in the groove. Should a defect be found in the original gasket, the gasket body can be removed from the groove of the concrete member relatively easily, even in the field, and a replacement gasket having corresponding anchor members can be snapped into the groove.
    Type: Application
    Filed: January 15, 2019
    Publication date: July 25, 2019
    Applicant: Vertex, Inc.
    Inventors: William C. Andrick, Richard J. Bowers, Troy Davidson, James A. Westhoff
  • Patent number: 9934964
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Publication number: 20160225609
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Patent number: 9309607
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Publication number: 20140338589
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Patent number: 8823056
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Patent number: 8187379
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20120104461
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: January 12, 2012
    Publication date: May 3, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christopher Leitz, Christopher Vineis, Richard Westhoff, Vicky Yang, Matthew Currie
  • Patent number: 8129747
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Richard Westhoff, Vicky Yang, Matthew T. Currie, Christopher J. Vineis, Christopher Leitz
  • Publication number: 20110177681
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Patent number: 7955435
    Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 7, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20110012172
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 20, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christopher Leitz, Christopher Vineis, Richard Westhoff, Vicky Yang, Matthew Currie
  • Patent number: 7829442
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: November 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Richard Westhoff, Vicky K. Yang, Matthew T. Currie, Christopher Vineis, Christopher Leitz
  • Publication number: 20100206216
    Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
    Type: Application
    Filed: February 24, 2010
    Publication date: August 19, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Patent number: 7674335
    Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Patent number: 7615829
    Abstract: A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 10, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Westhoff
  • Patent number: 7594967
    Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: September 29, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
  • Publication number: 20080135830
    Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 12, 2008
    Applicant: AmberWave Systems Corporation
    Inventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky K. Yang, Christopher W. Leitz
  • Patent number: 7375385
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: May 20, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Richard Westhoff, Vicky Yang, Matthew Currie, Christopher Vineis, Christopher Leitz
  • Patent number: 7368308
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: May 6, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz