Patents by Inventor Richard Westhoff

Richard Westhoff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7332417
    Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: February 19, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky T. Yang, Christopher W. Leitz
  • Publication number: 20060174818
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Application
    Filed: March 9, 2006
    Publication date: August 10, 2006
    Applicant: AmberWave Systems
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew Currie, Christopher Vineis, Thomas Langdo
  • Patent number: 7049627
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: May 23, 2006
    Assignee: AmberWave Systems Corporation
    Inventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
  • Patent number: 7041170
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: May 9, 2006
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20060009012
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: September 15, 2005
    Publication date: January 12, 2006
    Applicant: AmberWave Systems Corporation
    Inventors: Christopher Leitz, Christopher Vineis, Richard Westhoff, Vicky Yang, Matthew Currie
  • Publication number: 20040214407
    Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.
    Type: Application
    Filed: January 27, 2004
    Publication date: October 28, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky K. Yang, Christopher W. Leitz
  • Publication number: 20040087117
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: August 22, 2003
    Publication date: May 6, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Christopher Leitz, Christopher Vineis, Richard Westhoff, Vicky Yang, Matthew Currie
  • Publication number: 20040075105
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 22, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Christopher Leitz, Christopher Vineis, Richard Westhoff, Vicky Yang, Matthew Currie
  • Publication number: 20040040493
    Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
    Type: Application
    Filed: October 10, 2002
    Publication date: March 4, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
  • Publication number: 20030230233
    Abstract: A method for minimizing particle generation during deposition of a graded Si1−xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1−xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Application
    Filed: March 19, 2003
    Publication date: December 18, 2003
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20030227029
    Abstract: A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 11, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Westhoff