Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining a pacing requirement for host requests based on one or more thresholds; setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement; and implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level.

Abstract: Embodiments include methods, systems and computer program products for managing a flash memory device. Aspects include monitoring a percentage of memory of the flash memory device that is in a ready to use state. Aspects also include operating the flash memory device in a first operating mode based on a determination that the percentage is greater than a first threshold value. Aspects further include operating the flash memory device in a second operating mode based on a determination that the percentage has fallen below the first threshold value. Aspects include operating the flash memory device in a third operating mode until the percentage exceeds the first threshold value based on a determination that the percentage has fallen below a second threshold value, which is lower than the first threshold value. The erasing of ready to erase memory block stripes is only performed during the third operating mode.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining a pacing requirement for host requests based on one or more thresholds; setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement; and implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level.

Abstract: Embodiments include methods, systems and computer program products for managing a flash memory device. Aspects include monitoring a percentage of memory of the flash memory device that is in a ready to use state. Aspects also include operating the flash memory device in a first operating mode based on a determination that the percentage is greater than a first threshold value. Aspects further include operating the flash memory device in a second operating mode based on a determination that the percentage has fallen below the first threshold value. Aspects include operating the flash memory device in a third operating mode until the percentage exceeds the first threshold value based on a determination that the percentage has fallen below a second threshold value, which is lower than the first threshold value. The erasing of ready to erase memory block stripes is only performed during the third operating mode.

Abstract: Techniques for persisting a logical address-to-virtual address table in a solid state storage device are presented. An example method includes receiving a request to write data to a logical block address (LBA) in a memory component of the solid state storage device. The data is written to a location identified by a virtual block address (VBA) in the solid state storage device. The VBA is stored in a rotating dump table in a reserved logical unit of the solid state storage device. A mapping between the LBA and the VBA is stored in a rotating journal table located in the reserved logical unit. The rotating journal table is buffered such that a number of journal entries are stored in a buffer until a threshold number of journal entries are committed to the rotating journal table. A pointer to a current address in the rotating journal is stored in the buffer.

Abstract: Techniques for persisting a logical address-to-virtual address table in a solid state storage device are presented. An example method includes receiving a request to write data to a logical block address (LBA) in a memory component of the solid state storage device. The data is written to a location identified by a virtual block address (VBA) in the solid state storage device. The VBA is stored in a rotating dump table in a reserved logical unit of the solid state storage device. A mapping between the LBA and the VBA is stored in a rotating journal table located in the reserved logical unit. The rotating journal table is buffered such that a number of journal entries are stored in a buffer until a threshold number of journal entries are committed to the rotating journal table. A pointer to a current address in the rotating journal is stored in the buffer.

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

Abstract: A storage subsystem records a copy of a data object on a plurality of storage devices. The storage subsystem receives a read request to read a data object. Under certain utilization conditions of the storage subsystem, a resource utilization condition satisfies a split-read criterion. In response to the resource utilization condition satisfying the split-read criterion, the storage subsystem reads at least a portion of the data object from each of the storage devices having a copy of the data object.

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs cache line updates for writes, reads, and destages from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs writes to storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages cache line updates for purges from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.