Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs a host read and a cache destage simultaneously from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

Abstract: A storage subsystem records a copy of a data object on a plurality of storage devices. The storage subsystem receives a read request to read a data object. Under certain utilization conditions of the storage subsystem, a resource utilization condition satisfies a split-read criterion. In response to the resource utilization condition satisfying the split-read criterion, the storage subsystem reads at least a portion of the data object from each of the storage devices having a copy of the data object.

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs a host read and a cache destage simultaneously from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages cache line updates for purges from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs cache line updates for writes, reads, and destages from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs writes to storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.

Abstract: A method, system and computer program product are provided for implementing enhanced data caching and takeover of non-owned storage devices in a computer system. Each of a first controller and a second controller has a cache memory. During normal run-time, each storage device controller validates cached write data after it is written to its cache memory by reading the write data from its cache memory. If any error is detected on the read, then unit check failed storage device controller, which results in a reset of the failed storage device controller. When a storage device controller detects its dual partner controller fails, the surviving storage device controller queues host read/write operations for its storage devices already owned, and tests a cache mirrored copy from its cache memory of the failed first storage device controller before takeover of the failed controller's storage devices.

Abstract: A method and controller for implementing hardware auto device op initiator in a data storage system, and a design structure on which a subject controller circuit resides are provided. The controller includes an inline hardware engine receiving host commands, and assessing a received command for starting without firmware involvement. The inline hardware engine builds one or more chains of hardware command blocks to perform the received command and starts executing the chain or chains for the received command.