Abstract: A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.

Abstract: An integrated fluxgate device has a magnetic core disposed over a semiconductor substrate. A first winding is disposed in a first metallization level above and a second metallization level below the magnetic core, and is configured to generate a first magnetic field in the magnetic core. A second winding is disposed in the first and second metallization levels and is configured to generate a second magnetic field in the magnetic core. A third winding is disposed in the first and second metallization levels and is configured to sense a magnetic field in the magnetic core that is the net of the first and second magnetic fields.

Abstract: An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

Abstract: An electronic device comprises: a molybdenum layer; a bond pad formed on the molybdenum layer, the bond pad comprising aluminum; and a wire bonded to the bond pad, the wire comprising gold.

Abstract: In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.

Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.

Abstract: A fluxgate device that includes a first magnetic core and a second magnetic core. The first magnetic core has a first magnetized direction that deviates from a first sense direction by more than 0 degree and less than 90 degrees. The second magnetic core is arranged orthogonally to the first magnetic core. The second magnetic core has a second magnetized direction that deviates from a second sense direction by more than 0 degree and less than 90 degrees.

Abstract: Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Abstract: The dominant frequency of a solidly mounted resonator (100/280/300/400) is substantially increased by reducing the thickness of each layer of each Bragg acoustic reflector (112/160/224/274) to have a thickness than is substantially equal to one-quarter of the wavelength of a frequency that is a higher harmonic resonant frequency of the fundamental resonant frequency of the solidly mounted resonator (100/280/300/400).

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Abstract: Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.

Abstract: An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Abstract: A fluxgate device that includes a first magnetic core and a second magnetic core. The first magnetic core has a first magnetized direction that deviates from a first sense direction by more than 0 degree and less than 90 degrees. The second magnetic core is arranged orthogonally to the first magnetic core. The second magnetic core has a second magnetized direction that deviates from a second sense direction by more than 0 degree and less than 90 degrees.

Abstract: An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated circuit dies arranged in rows and columns and spaced apart by the scribe streets. Each integrated circuit die includes plurality of active areas; a plurality of insulator layers overlying the active areas; a plurality of conductor layers interspersed with and separated by ones of the insulator layers; and a passivation layer overlying a top portion of the uppermost one of the conductor layers. A scribe seal in a scribe region surrounds the periphery of the integrated circuit dies, the scribe seal covered by the passivation layer; and a crack arrest structure is located surrounding and spaced from the scribe seal, and including an opening in the passivation layer that extends to and exposes the upper surface of the crack arrest structure. Methods are disclosed.

Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.

Abstract: A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer.

Abstract: A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.

Abstract: The dominant frequency of a solidly mounted resonator (100/280/300/400) is substantially increased by reducing the thickness of each layer of each Bragg acoustic reflector (112/160/224/274) to have a thickness than is substantially equal to one-quarter of the wavelength of a frequency that is a higher harmonic resonant frequency of the fundamental resonant frequency of the solidly mounted resonator (100/280/300/400).