Patents by Inventor Rie Takada

Rie Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9117788
    Abstract: A method of repairing a semiconductor device includes turning a press member to apply pressure on an electronic component which is mounted on a substrate. A heat sink which is provided on the electronic component via a bonding layer is thus displaced with respect to the electronic component in a transverse direction. The heat sink is removed from the electronic component by shearing the bonding layer with the press member.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: August 25, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Yamamoto, Naoaki Nakamura, Rie Takada, Kenichiro Tsubone, Yasuhide Kuroda, Harumi Yagi
  • Publication number: 20120083151
    Abstract: A method of detachment of a connector which is provided with a housing having connector pins to be inserted into a board and with a first member which is arranged between the housing and the board and through which the connector pins are inserted, the method including a process of pulling out the connector pins from the board. This process utilizes the lever principle, which uses the first member as a fulcrum and which uses any point on the housing as a point of action, so as to pull out the connector pins from the board.
    Type: Application
    Filed: July 19, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Rie TAKADA, Tsuyoshi YAMAMOTO, Naoaki NAKAMURA, Harumi YAGI
  • Publication number: 20120024512
    Abstract: A method of repairing a semiconductor device includes turning a press member to apply pressure on an electronic component which is mounted on a substrate. A heat sink which is provided on the electronic component via a bonding layer is thus displaced with respect to the electronic component in a transverse direction. The heat sink is removed from the electronic component by shearing the bonding layer with the press member.
    Type: Application
    Filed: July 18, 2011
    Publication date: February 2, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Yamamoto, Naoaki Nakamura, Rie Takada, Kenichiro Tsubone, Yosuhide Kuroda, Harumi Yagi
  • Publication number: 20110240719
    Abstract: In the initial state, a part having a bottom electrode such as a BGA is attached to a substrate. A heat transfer material such as low melting point solder is allowed to fill a gap between the substrate and the part having the bottom electrode, and the heat transfer material and the BGA serving as the bottom electrode are heated. The heat transfer material and the BGA are melted by the heating so that the part having the bottom electrode is removed from the substrate.
    Type: Application
    Filed: February 11, 2011
    Publication date: October 6, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Rie TAKADA, Tsuyoshi YAMAMOTO
  • Publication number: 20110031628
    Abstract: A semiconductor device module includes a first substrate layer on which a first semiconductor device is surface-mounted, a second substrate layer that is a layer laminated on a side of the first substrate layer on which the first semiconductor device is not surface-mounted, a second semiconductor device being surface-mounted on a surface of the second substrate layer and not on a side of the first substrate layer, and a hollow section that is a space sandwiched between the first substrate layer and the second substrate layer and formed on back sides of areas on which the first semiconductor device and the second semiconductor device are surface-mounted.
    Type: Application
    Filed: July 22, 2010
    Publication date: February 10, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Rie TAKADA
  • Publication number: 20110007482
    Abstract: A printed circuit board unit includes a printed circuit board including through holes arranged in a grid array on which an integrated circuit is mounted; and a flexible substrate provided on a back side of the printed circuit board, covering the through holes. First lands to which the integrated circuit is connected are formed on a front side of the printed circuit board. Second lands to which the flexible substrate is connected are formed on the back side of the printed circuit board. The first lands and the second lands are connected to first ends and second ends of the through holes, respectively. Third lands are formed on a front side of the flexible substrate so as to face the second lands of the printed circuit board. Fourth lands are formed on a back side of the flexible substrate. The fourth lands are electrically connected to the third lands.
    Type: Application
    Filed: June 23, 2010
    Publication date: January 13, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Rie Takada, Kenichiro Tsubone
  • Publication number: 20100214741
    Abstract: An electronic component mounting structure includes a first substrate on which a first component is mounted and a second substrate connected to the first substrate. The second substrate is bent toward the first component.
    Type: Application
    Filed: December 7, 2009
    Publication date: August 26, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Rie Takada, Kenichiro Tsubone
  • Publication number: 20090020588
    Abstract: A method for manufacturing a product involving solder joining wherein components placed on a board on which the components are to be mounted are solder-joined to the board by subjecting the board to reflow heating under prescribed heating conditions, the method comprising: calculating, at each designated site on the board, a component volume that is occupied by the components mounted within a given area; determining the heating conditions in accordance with the calculated component volume; and performing the reflow heating based on the determined heating conditions.
    Type: Application
    Filed: September 16, 2008
    Publication date: January 22, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Osamu Saito, Rie Takada, Mitsumasa Kojima, Tetsuji Ishikawa
  • Publication number: 20060231541
    Abstract: A heater that attaches an electronic component having a ball grid array structure to and detaches the electronic component from a substrate on which the electronic component operates includes a body fixed onto the electronic component, and a heating element, provided on the body, which heats and melts soldering balls having the ball grid array structure when receiving power supply.
    Type: Application
    Filed: July 29, 2005
    Publication date: October 19, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Rie Takada, Kenichiro Tsubone
  • Patent number: 6866549
    Abstract: The present invention relates to an electrical connector assembly capable of achieving a high-precision fit starting with fairly rough positioning, the assembly consisting of a first connector which is equipped with multiple substrates secured in an array and a second connector which is equipped with female terminals and mates with the first connector. The electrical connector has a rough guide mechanism (first guides and second guides as well as first complementary guides and second complementary guides) which guides a mating between the first connector and the second connector relatively roughly at an initial stage of mating, and a precision guide mechanism (chamfers on substrates and corresponding tapers on a housing of the second connector) which guides the mating between the first connector and the second connector relatively precisely at an advanced stage of mating.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: March 15, 2005
    Assignees: Tyco Electronics AMP K.K., Fujitsu Limited
    Inventors: Takeshi Kimura, Kazuya Orui, Kunihiko Shimizu, Hiroyuki Otaguro, Rie Takada
  • Publication number: 20040185716
    Abstract: The present invention relates to an electrical connector assembly capable of achieving a high-precision fit starting with fairly rough positioning, the assembly consisting of a first connector which is equipped with multiple substrates secured in an array and a second connector which is equipped with female terminals and mates with the first connector. The electrical connector has a rough guide mechanism (first guides and second guides as well as first complementary guides and second complementary guides) which guides a mating between the first connector and the second connector relatively roughly at an initial stage of mating, and a precision guide mechanism (chamfers on substrates and corresponding tapers on a housing of the second connector) which guides the mating between the first connector and the second connector relatively precisely at an advanced stage of mating.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 23, 2004
    Inventors: Takeshi Kimura, Kazuya Orui, Kunihiko Shimizu, Hiroyuki Otaguro, Rie Takada
  • Publication number: 20040185715
    Abstract: The present invention is an electrical connector, having multiple terminals equipped with compliant sections to be inserted into through-holes in a main board; multiple sub-boards equipped with lands connected to the terminals and a contact section to be connected to a mating connector. The lands consist of a conductor formed on an insulator and a housing used to secure the multiple sub-boards in an array, wherein owing to a conductor which extends close to the terminal-side edge of the insulator, the lands prevent the sub-boards from being buckled by being bitten by the terminals when the compliant sections are inserted into the through-holes in the main board.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 23, 2004
    Inventors: Takeshi Kimura, Kazuya Orui, Kunihiko Shimizu, Hiroyuki Otaguro, Rie Takada
  • Patent number: 6216342
    Abstract: A method for fabricating a matrix switch board used for connecting and disconnecting a switching-system line and a subscriber line. The matrix switch board is formed to include a board made of an insulating material, first and second wiring patterns respectively formed on front and back sides of the board so as to cross each other, and through holes provided at cross points of the first and second wiring patterns. A connection pin inserted into at least one of the through holes, electrically connects at least one of the first wiring patterns on the front side and at least one of the second wiring patterns on the back side.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventors: Masao Hosogai, Setuo Kojima, Hitoshi Yokemura, Rie Takada, Hiroyuki Otaguro, Takayuki Ashida, Toshio Abe
  • Patent number: 6116912
    Abstract: A matrix switch board used for connecting and disconnecting a switching-system line and a subscriber line. The matrix switch board includes a board made of an insulating material, and first and second wiring patterns respectively formed on front and back sides of the board so as to cross each other. The matrix switch board further includes through holes provided at cross points of the first and second wiring patterns. In the matrix switch board, when a connection pin is inserted into at least one of the through holes, at least one of the first wiring patterns on the front side and at least one of the second wiring patterns on the back side are electrically connected to each other.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: September 12, 2000
    Assignee: Fujitsu Limited
    Inventors: Masao Hosogai, Setuo Kojima, Hitoshi Yokemura, Rie Takada, Hiroyuki Otaguro, Takayuki Ashida, Toshio Abe
  • Patent number: D443888
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: June 19, 2001
    Assignee: Fuji Xerox Co. LTD
    Inventors: Hiroshi Nakada, Masaaki Takenouchi, Rie Takada, William T. Clark
  • Patent number: D445449
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: July 24, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Masaaki Takenouchi, Rie Takada, Hiroshi Nakada, William T. Clark
  • Patent number: D547367
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 24, 2007
    Assignee: Xerox Corporation
    Inventors: William T. Clark, III, Rie Takada
  • Patent number: D431592
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: October 3, 2000
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Masaaki Takenouchi, Rie Takada, Hiroshi Nakada, William T. Clark
  • Patent number: D431594
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: October 3, 2000
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shu Watanabe, Hiroshi Nakada, Masaaki Takenouchi, Rie Takada, Donald Brown
  • Patent number: D433440
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: November 7, 2000
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Masaaki Takenouchi, Rie Takada, Hiroshi Nakada, William T. Clark