Patents by Inventor Rieko FUNATSUKI

Rieko FUNATSUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240062822
    Abstract: A semiconductor memory device includes a first to eighth memory cell groups arranged along a first direction, a first word line extending in the first direction and a first to an eighth sense amplifier groups configured to be capable of supplying voltages to the first to the eighth memory cell groups, respectively. Each of the first to the eighth memory cell groups includes a plurality of memory cells and a plurality of bit lines each connected to the plurality of memory cells. In a write operation of supplying a program voltage to the first word line, the first sense amplifier group supplies a first voltage to the bit line connected to a write target memory cell of the first memory cell group, and the second sense amplifier group supplies a second voltage to the bit line connected to a write target memory cell of the second memory cell group.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Applicant: Kioxia Corporation
    Inventors: Rieko FUNATSUKI, Takashi MAEDA
  • Publication number: 20230413584
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Takahiko IIZUKA, Daisaburo TAKASHIMA, Ryu OGIWARA, Rieko FUNATSUKI, Yoshiki KAMATA, Misako MOROTA, Yoshiaki ASAO, Yukihiro NOMURA
  • Patent number: 11769554
    Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: September 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Kyosuke Sano, Kazutaka Ikegami, Takashi Maeda, Rieko Funatsuki
  • Publication number: 20230297245
    Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 21, 2023
    Inventors: Rieko FUNATSUKI, Takashi MAEDA, Sumiko DOMAE, Kazutaka IKEGAMI
  • Patent number: 11765916
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara, Rieko Funatsuki, Yoshiki Kamata, Misako Morota, Yoshiaki Asao, Yukihiro Nomura
  • Patent number: 11715527
    Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventors: Kazutaka Ikegami, Hidehiro Shiga, Takashi Maeda, Rieko Funatsuki, Takayuki Miyazaki
  • Patent number: 11715534
    Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventors: Rieko Funatsuki, Takashi Maeda, Reiko Sumi, Reika Tanaka, Masumi Saitoh
  • Publication number: 20230197148
    Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.
    Type: Application
    Filed: June 10, 2022
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventors: Rieko FUNATSUKI, Takashi MAEDA, Hidehiro SHIGA
  • Publication number: 20220301636
    Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Kyosuke SANO, Kazutaka IKEGAMI, Takashi MAEDA, Rieko FUNATSUKI
  • Publication number: 20220301643
    Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.
    Type: Application
    Filed: August 27, 2021
    Publication date: September 22, 2022
    Inventors: Rieko FUNATSUKI, Takashi MAEDA, Reiko SUMI, Reika TANAKA, Masumi SAITOH
  • Publication number: 20220180942
    Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.
    Type: Application
    Filed: August 26, 2021
    Publication date: June 9, 2022
    Inventors: Kazutaka IKEGAMI, Hidehiro SHIGA, Takashi MAEDA, Rieko FUNATSUKI, Takayuki MIYAZAKI
  • Publication number: 20220093152
    Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.
    Type: Application
    Filed: March 15, 2021
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Reika TANAKA, Masumi SAITOH, Takashi MAEDA, Rieko FUNATSUKI, Hidehiro SHIGA
  • Patent number: 11282578
    Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Rieko Funatsuki, Takahiko Hara, Takashi Maeda
  • Patent number: 11282559
    Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Reika Tanaka, Masumi Saitoh, Takashi Maeda, Rieko Funatsuki, Hidehiro Shiga
  • Publication number: 20210399049
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Takahiko IIZUKA, Daisaburo TAKASHIMA, Ryu OGIWARA, Rieko FUNATSUKI, Yoshiki KAMATA, Misako MOROTA, Yoshiaki ASAO, Yukihiro NOMURA
  • Patent number: 11200951
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 14, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Rieko Funatsuki, Takahiko Sasaki, Tomonori Kurosawa
  • Patent number: 11049573
    Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 29, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Rieko Funatsuki, Takashi Maeda, Hidehiro Shiga, Hiroshi Maejima
  • Publication number: 20210090665
    Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.
    Type: Application
    Filed: June 19, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Rieko FUNATSUKI, Takahiko HARA, Takashi MAEDA
  • Publication number: 20200395084
    Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.
    Type: Application
    Filed: February 26, 2020
    Publication date: December 17, 2020
    Inventors: Rieko FUNATSUKI, Takashi MAEDA, Hidehiro SHIGA, Hiroshi MAEJIMA
  • Publication number: 20200185035
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.
    Type: Application
    Filed: September 5, 2019
    Publication date: June 11, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Rieko FUNATSUKI, Takahiko Sasaki, Tomonori KUROSAWA