Patents by Inventor Rieko FUNATSUKI
Rieko FUNATSUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049573Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.Type: GrantFiled: February 26, 2020Date of Patent: June 29, 2021Assignee: KIOXIA CORPORATIONInventors: Rieko Funatsuki, Takashi Maeda, Hidehiro Shiga, Hiroshi Maejima
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Publication number: 20210090665Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.Type: ApplicationFiled: June 19, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Rieko FUNATSUKI, Takahiko HARA, Takashi MAEDA
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Publication number: 20200395084Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.Type: ApplicationFiled: February 26, 2020Publication date: December 17, 2020Inventors: Rieko FUNATSUKI, Takashi MAEDA, Hidehiro SHIGA, Hiroshi MAEJIMA
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Publication number: 20200185035Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.Type: ApplicationFiled: September 5, 2019Publication date: June 11, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Rieko FUNATSUKI, Takahiko Sasaki, Tomonori KUROSAWA
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Patent number: 10553276Abstract: A semiconductor memory device includes a memory cell array, a first data latch that retains a write unit of data to be written to the memory cell array, a first address latch that retains a write address indicating a write target destination for the write unit of data in the first data latch, a second data latch that retains fail data that is a write unit of data that has failed to be written to the memory cell array, and a second address latch that retains a fail address indicating a write target destination for the fail data. A controller is configured to output the fail address from the second address latch in response to a first output command requesting output of the fail address and to output the fail data from the second data latch in response to a second output command requesting an output of the fail data.Type: GrantFiled: February 26, 2018Date of Patent: February 4, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Rieko Funatsuki
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Patent number: 10332593Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.Type: GrantFiled: December 16, 2016Date of Patent: June 25, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahiko Sasaki, Go Shikata, Tomonori Kurosawa, Rieko Funatsuki
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Publication number: 20190066782Abstract: A semiconductor memory device includes a memory cell array, a first data latch that retains a write unit of data to be written to the memory cell array, a first address latch that retains a write address indicating a write target destination for the write unit of data in the first data latch, a second data latch that retains fail data that is a write unit of data that has failed to be written to the memory cell array, and a second address latch that retains a fail address indicating a write target destination for the fail data. A controller is configured to output the fail address from the second address latch in response to a first output command requesting output of the fail address and to output the fail data from the second data latch in response to a second output command requesting an output of the fail data.Type: ApplicationFiled: February 26, 2018Publication date: February 28, 2019Inventor: Rieko FUNATSUKI
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Publication number: 20170110186Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.Type: ApplicationFiled: December 16, 2016Publication date: April 20, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takahiko Sasaki, Go Shikata, Tomonori Kurosawa, Rieko Funatsuki
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Patent number: 9305637Abstract: A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.Type: GrantFiled: March 2, 2014Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Rieko Funatsuki, Takuya Futatsuyama, Fumitaka Arai
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Publication number: 20160005459Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Rieko FUNATSUKI, Koichi FUKUDA
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Publication number: 20150070989Abstract: A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.Type: ApplicationFiled: March 2, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Rieko FUNATSUKI, Takuya FUTATSUYAMA, Fumitaka ARAI
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Patent number: 8830760Abstract: A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.Type: GrantFiled: February 20, 2013Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Rieko Funatsuki, Osamu Nagao
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Publication number: 20140241057Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation.Type: ApplicationFiled: August 14, 2013Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Rieko FUNATSUKI, Koichi Fukuda
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Publication number: 20140050028Abstract: A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.Type: ApplicationFiled: February 20, 2013Publication date: February 20, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Rieko FUNATSUKI, Osamu Nagao