Patents by Inventor Rinji Sugino
Rinji Sugino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8809206Abstract: A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.Type: GrantFiled: February 7, 2011Date of Patent: August 19, 2014Assignee: Spansion LLCInventors: Rinji Sugino, Bradley Marc Davis, Lei Xue, Kenichi Ohtsuka
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Publication number: 20140138790Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: Spansion LLCInventors: Rinji SUGINO, Fei WANG
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Publication number: 20140134332Abstract: A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: Spansion LLCInventor: Rinji SUGINO
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Patent number: 8647969Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.Type: GrantFiled: January 31, 2012Date of Patent: February 11, 2014Assignee: Spansion LLCInventors: Rinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey Sinclair Glick, Kuo Tung Chang
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Publication number: 20130228851Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: ApplicationFiled: April 8, 2013Publication date: September 5, 2013Applicant: SPANSION LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Patent number: 8455268Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.Type: GrantFiled: August 31, 2007Date of Patent: June 4, 2013Assignee: Spansion LLCInventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu
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Patent number: 8415734Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: GrantFiled: December 7, 2006Date of Patent: April 9, 2013Assignee: Spansion LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Publication number: 20120202355Abstract: A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.Type: ApplicationFiled: February 7, 2011Publication date: August 9, 2012Applicant: Spansion LLCInventors: Rinji Sugino, Bradley Marc Davis, Lei Xue, Kenichi Ohtsuka
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Patent number: 8143661Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.Type: GrantFiled: October 10, 2006Date of Patent: March 27, 2012Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Patent number: 8133801Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.Type: GrantFiled: July 27, 2005Date of Patent: March 13, 2012Assignee: Spansion LLCInventors: Rinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey Sinclair Glick, Kuo-Tung Chang
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Publication number: 20110272775Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.Type: ApplicationFiled: July 14, 2011Publication date: November 10, 2011Inventors: Eunha KIM, Jeremy WAHL, Shenqing FANG, YouSeok SUH, Kuo-Tung CHANG, Yi MA, Rinji SUGINO, Jean YANG
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Patent number: 7998846Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.Type: GrantFiled: September 12, 2008Date of Patent: August 16, 2011Assignee: Spansion LLCInventors: Eunha Kim, Jeremy Wahl, Shenqing Fang, YouSeok Suh, Kuo-Tung Chang, Yi Ma, Rinji Sugino, Jean Yang
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Publication number: 20100065940Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.Type: ApplicationFiled: September 12, 2008Publication date: March 18, 2010Inventors: Eunha KIM, Jeremy WAHL, Shenqing FANG, YouSeok SUH, Kuo-Tung CHANG, Yi MA, Rinji SUGINO, Jean YANG
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Publication number: 20090269916Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Inkuk KANG, Gang XUE, Shenqing FANG, Rinji SUGINO, Yi MA
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Publication number: 20090261406Abstract: A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. More specifically, the ratio of silicon-to-nitrogen in the first layer is greater than the ratio of silicon-to-nitrogen in the second layer.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Inventors: Youseok SUH, Shenqing FANG, Kuo Tung CHANG, Rinji SUGINO, Yi MA, Eunha KIM
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Publication number: 20090061631Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.Type: ApplicationFiled: August 31, 2007Publication date: March 5, 2009Applicant: SPANSION LLCInventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu
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Publication number: 20080142874Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.Type: ApplicationFiled: December 16, 2006Publication date: June 19, 2008Applicants: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Hidehiko Shiraiwa, Takayuki Maruyama, Kuo-Tung Chang, YouSeok Suh, Amol Ramesh Joshi, Harpreet Sachar, Simon Siu-Sing Chan
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Publication number: 20080135913Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: ApplicationFiled: December 7, 2006Publication date: June 12, 2008Applicant: Spansion LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Publication number: 20080083946Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Patent number: 7354826Abstract: According to one exemplary embodiment, a method of fabricating a bitline in a memory array includes forming a trench in a substrate, where the trench has sidewalls and a bottom surface. The method further includes performing a selective epitaxial process to partially fill the trench with selective epitaxially grown silicon, where the selective epitaxially grown silicon is situated on the sidewalls and bottom surface of the trench. The selective epitaxially grown silicon is doped in the selective epitaxial process. The method further includes performing a silicon reflow process to cause the selective epitaxially silicon to be redistributed in the trench. The method further includes performing a number of selective epitaxial process/silicon reflow process cycles to substantially fill the trench with the selective epitaxially grown silicon. The method further includes extending a top surface of the selective epitaxially grown silicon in the trench above an ONO stack to form the bitline.Type: GrantFiled: April 22, 2005Date of Patent: April 8, 2008Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Takashi Orimoto, Robert B. Ogle, Rinji Sugino