Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same
A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.
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1. Technical Field
This disclosure relates generally to improved semiconductor products that employ air gaps as inter-layer insulators, and methods and apparatus for making such semiconductor products.
2. Related Art
Modern semiconductor devices comprise vast numbers of individual structures or components disposed on one or more layers. To ensure that a semiconducting device functions properly, most, if not all, of the individual structures or components need to be electrically isolated from each other. Traditionally, such isolation is accomplished through the use of materials such as dielectric films to act as inter-layer insulators between the various components that make up a typical device. However, as device size decreases, the existing materials have been found to result in a number of problems such as leakage, noise, and a capacitive effect, for example. One approach used to ameliorate the problems associated with the use of dielectric materials as insulators has been to instead use air gaps as insulators.
Existing methods for forming air gaps and using them as insulation have drawbacks. For instance, existing methods of air-gap formation rely on the so-called “pinching method” whereby a non-conformal (i.e., uneven) film deposition over structures of a semiconducting device is used to create an air gap. In short, this works by depositing the dielectric film more thickly at the top of the structures and more thinly towards the base of the structure. When two structures are adjacent to each other, the thick parts of the film touch at a “pinch point” thereby closing off an air gap beneath the pinch point. However, air gaps created through the pinching method still suffer from various problems. For instance, such air gaps can have problems associated with noise coupling and leakage through pinching portions. Additionally, the pinching method is dependent on the physical layout of the structures that form the semiconductor device; malformed air gaps can be produced when the individual structures are too close or too far from one another. There are also other uncontrollable aspects of the deposition process and the fabrication process that can result in malformed air gaps. Accordingly, new devices and methods as well as method and apparatuses for producing such devices that do not suffer from the same drawbacks as the existing methods are desired.
BRIEF SUMMARY OF THE INVENTIONEmbodiments of the invention include apparatuses and methods of producing semiconductor devices that use an gaps as electrical insulators. Embodiments also include such semiconductor devices. According to some embodiments, the method may include forming a sacrificial layer between a first structure and a second structure. A membrane layer can be formed over the sacrificial layer. Preferably, the membrane can be porous to an etch product. The sacrificial layer may then be etched away to create an air gap without etching the membrane layer or the buffer layer. A cap layer may be disposed on top of the membrane layer according to various embodiments. According to some embodiments, a buffer layer may be formed between the sacrificial layer and the first and second structures.
According to some embodiments of the invention, a semiconducting device that uses air gaps as electrical insulators is provided. The device may include an air gap insulator disposed between a first and second structure of the semiconducting device. The device also includes a membrane layer disposed above the air gap and between the first and second structures. The membrane layer is porous to an etching product that is capable of etching the sacrificial layer without etching the membrane layer. According to various embodiments, the device may also include a cap layer disposed on top of the membrane layer. A buffer layer may be formed between the first and second structures and the air gap.
Further features and advantages of embodiments of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only Additional embodiments will be apparent to a person skilled in the relevant art(s) based on the teachings contained herein.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts. Further, the accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present invention, and, together with the description, further serve to, explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.
The features and advantages of embodiments of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.
DETAILED DESCRIPTION OF THE INVENTIONThe following detailed description refers to the accompanying drawings that illustrate exemplary embodiments consistent with this invention. Other embodiments are possible, and modifications can be made to the embodiments within the spirit and scope of the invention. Therefore, the detailed description is not meant to limit the invention. Rather, the scope of the invention is defined by the appended claims.
As shown in
Stated another way, there is no pinch point associated with air gap 110a because the distance between structure 104a and 104b is greater than the thickness of the buffer layer 106 covering structures 104a and 104b. Thus, the buffer layer 106 cannot “pinch” at a pinch point. As can be seen, the “pinching” method is dependent, to a certain extent, on the physical dimensions of the various structures 104 that comprise the semiconducting device 100. While gap 110a does constitute an air gap and it can insulate structure 104a from 104b, the open top can sometimes foreclose the possibility of another layer, such as a cap layer, being formed over the gap 110a at point 108a. As depicted in
Semiconductor 200 was formed using a manufacturing process according to embodiments of the present invention.
The structures 204 are disposed on a base 202, which may comprise a semiconducting substrate, the top of another layer of device components, or the like. Additionally, gaps 210a and 210b (collectively referred to as gaps 210, herein) are positioned between structures 204a and 204b and between structures 204b and 204c, respectively.
As shown in
Thus, as can be seen in
At step 304, a sacrificial layer 208 is deposited on top of the buffer layer 206 and between device structures 204 (
At step 306, the excess sacrificial layer 208 is removed by, for instance, polishing or etching (
At step 308, the membrane layer 212 can be formed over the remaining portion of the sacrificial layer 208 (
At step 310, the sacrificial layer 208 can be removed from the device 200 by selective etching thereby leaving air gaps 210 in the spaces 210 once occupied by the sacrificial layer 208 (
At step 312, a cap layer is formed or top of the membrane layer the cap layer 214 can be employed to deal the air gaps. According to various embodiments, the cap layer 214 can be used for any material and process such as CVD of SiO2, sputtered Al2O3, or SiN by high viscosity liquid source. While, in an embodiment, the cap layer 214 comprises a dielectric material, it may sometimes be desirable to form it of metal layers, depending on the various requirements.
The fabrication module 404 can include semiconductor fabrication equipment of any number of well-known types. The control module 402 can contain computer instructions, that when executed, cause control signals to be sent to the fabrication module 404 via the communication link 406. The control signals can cause the fabrication module 404 to produce a semiconducting device according to method 300 depicted in
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.
Embodiments of the present invention have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims
1. A method of forming an air-gap in a semiconducting device, comprising:
- forming a sacrificial layer between a first structure and a second structure;
- forming a membrane layer over the sacrificial layer, the membrane being porous to an etch product; and
- etching the sacrificial layer through the membrane and between the first structure and the second structure to create an air gap, wherein the sacrificial layer is etched without etching the membrane layer.
2. The method of claim 1, further comprising forming a buffer layer between the sacrificial layer and the first and second structures.
3. The method of claim 1, further comprising forming a cap layer above the membrane layer.
4. The method of claim 3, wherein the cap layer comprises a dielectric material.
5. The method of claim 1, further comprising planerizing the sacrificial layer prior to forming the membrane material.
6. The method of claim 1, wherein the membrane layer is formed such that it overlaps a portion of the first structure and a portion of the second structure.
7. The method of claim 1, wherein the air gap functions as an insulator between the first and second structures.
8. The method of claim 1, wherein at least one of the first and second structures comprises a transistor, a capacitor, an electrode, a contact, or an interconnect.
9. The method of claim 1, wherein the membrane layer is formed by sputtering or deposition.
10. The method of claim 1, wherein the sacrificial layer comprises Silicon, Aluminum, Germanium, Tungsten, photo resist, or an organic film.
11. A semiconducting device, comprising:
- a first structure and a second structure;
- an air gap disposed between the first structure and the second structure; and
- a membrane layer disposed above the air gap and between the first and second structures, wherein the membrane layer is porous to an etching product, the etching product being capable of etching a sacrificial layer without etching the membrane layer.
12. The device of claim 11, further comprising a buffer layer disposed between the membrane layer and the first and second structures.
13. The device of claim 11, further comprising a cap layer disposed above the membrane layer.
14. The device of claim 13, wherein the cap layer comprises a dielectric material.
15. The device of claim 11, wherein the membrane layer comprises a native oxide.
16. The device of claim 11, wherein the membrane layer overlaps a portion of the first structure and a portion of the second structure.
17. The device of claim 11, wherein the air gap functions as an insulator between the first and second structures.
18. The device of claim 11, wherein one of the first and second structures comprises a transistor, a capacitor, an electrode, a contact, or an interconnect.
19. The device of claim 11, wherein the membrane layer is formed by sputtering or deposition.
20. The device of claim 11, wherein membrane layer is configured to be permeable to an etching product that etches Silicon, Aluminum, Germanium, Tungsten, photo resist, or an organic film.
21. An apparatus, comprising:
- a semiconductor fabrication module; and
- a semiconductor fabrication controller configured to cause the semiconducting fabrication module to: form a sacrificial layer between a first structure and a second structure of a semiconductor device; form a membrane layer over the sacrificial layer, the membrane being porous to an etch product; and etch the sacrificial layer through the membrane and between the first structure and the second structure to create an air gap, wherein the sacrificial layer is etched without etching the membrane layer.
22. A semiconducting device, comprising:
- a first structure and a second structure;
- an air gap disposed between the first structure and the second structure;
- a membrane layer disposed above the air gap and between the first and second structures, wherein the membrane layer is porous to an etching product, the etching product being capable of etching a sacrificial layer without etching the membrane layer; and
- a buffer layer disposed on the first and second structures, wherein the buffer layer is configured to not react with the etching product and to act as a protective layer with respect to the first and second structures.
Type: Application
Filed: Nov 21, 2012
Publication Date: May 22, 2014
Applicant: Spansion LLC (Sunnyvale, CA)
Inventors: Rinji SUGINO (San Jose, CA), Fei WANG (San Jose, CA)
Application Number: 13/682,826
International Classification: H01L 21/764 (20060101); H01L 29/06 (20060101);