Abstract: Embodiments provide methods and systems for facilitating scheduled payment transactions to users via an application provided by the server system, the application available on the user device. The method performed by the server system includes receiving a transaction request message from the user device, the transaction request message includes scheduled transaction instruction provided by the user in natural language format. The method includes authenticating the user based on a plurality of user authentication factors received from the user at pre-defined time intervals. In an embodiment, the server system is configured to train a data model using ML algorithms by learning the plurality of user authentication factors based on which the user is automatically authenticated by the server system. Upon successful authentication, the method includes parsing the transaction request message to determine a scheduled transaction instruction.

Abstract: The present disclosure provides systems and methods for synthesizing computer-readable code based on the receipt of input and output examples. A computing system in accordance with the disclosure can be configured to receive a given input and output, access and library of operations, and perform a search of a library of operations (e.g., transpose, slice, norm, etc.) that can be applied to the input. By applying the operations to the input and tracking the results, the computing system may identify an expression comprising one or a combination of operations that when applied to the input generates the output. In this manner, implementations of the disclosure may be used to identify one or more solutions that a user having access to the library of operations may use to generate the output from the input.

Abstract: An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.

Abstract: An embodiment may involve, based on a profile associated with a client device, selecting an audio file containing music. Based on an attribute of the audio file containing the music, an audio file containing a story may be selected. A playlist for the client device may be generated, where the playlist includes (i) a reference to the audio file containing the music, and (ii) a reference to the audio file containing the story. A server device may transmit the playlist to the client device over a wide area network. Reception of the playlist at the client device may cause an audio player application to retrieve and play out each of the audio file containing the music and the audio file containing the story.

Abstract: Techniques for facilitating returns of ordered items include receiving, by a control device, a first code associated with an order, determining that the code corresponds to a valid order, and granting access to a controlled access area where a user may examine the ordered items. If a second code associated with a particular item is received by the control device, a determination is made that the code corresponds to an item associated with the order, and access to a container within the controlled access area is granted. Once an item is placed in the container, sensors in the container determine characteristics of the item. If the determined characteristics correspond to item data that indicates the expected characteristics of the item, data indicative of a return of the item is generated.

Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

Abstract: Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

Abstract: A computer-implemented method for determining defect regions of products in a manufacturing process, is disclosed. The computer-implemented method includes steps of: obtaining experimental data from a machine; (b) obtaining first geometry data associated with historical products; (c) computing first geometrical parameters, based on the first geometry data associated with the historical products, by a geometry model; (d) computing second geometrical parameters, based on second geometry data associated with new products, by the geometry model; and (e) determining the defect regions in the new and historical products, based on the computed statistical features associated with defect types and locations, and the first and second geometrical parameters, by a machine learning model. The machine learning model is configured to determine the optimized recipe parameter to reduce the defect in at least one of: the new products and the historical products.

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.

Abstract: A control unit to map at least one element present in plurality of documents (i.e., a first document and a second document) is disclosed. The control unit identifies the at least one element in the plurality of documents and identifies at least one semantic bridge between the first document and the second document using string-based similarities. The control unit generates a corresponding taxonomy graph and a graph embedding for the at least one element of the first document and the second document. The control unit correlates the generated corresponding graph embeddings of the at least one element of the first document and the second document. The control unit maps the at least one element of the first document to the at least one element of the second document using a vector function.

Abstract: In implementations of systems for generating images for virtual try-on and pose transfer, a computing device implements a generator system to receive input data describing a first digital image that depicts a person in a pose and a second digital image that depicts a garment. Candidate appearance flow maps are computed that warp the garment based on the pose at different pixel-block sizes using a first machine learning model. The generator system generates a warped garment image by combining the candidate appearance flow maps as an aggregate per-pixel displacement map using a convolutional gated recurrent network. A conditional segment mask is predicted that segments portions of a geometry of the person using a second machine learning model. The generator system outputs a digital image that depicts the person in the pose wearing the garment based on the warped garment image and the conditional segmentation mask using a third machine learning model.

Abstract: A method for managing memory for applications in a computing system includes receiving a selection of a preferred application. During user-controlled operation over the application, the transitions of selected application between foreground and background are monitored. A retention of the application in memory is triggered upon a transition of the application to background during the user operation. Retention of the application includes compressing memory portions of the application. Accordingly, the application is retained within the memory based on said compressed memory portions. A requirement to restore the retained application is sensed based on either a user selection or an automatically generated prediction and the application is restored from the retained state back to the foreground.

Abstract: This specification is generally directed to techniques for robust natural language (NL) based control of computer applications. In many implementations, the NL control is at least selectively interactive in that the user feedback input is solicited, and received, in resolving action(s), resolving action set(s), generating domain specific knowledge, and/or in providing feedback on implemented action set(s). The user feedback input can be utilized in further training of machine learning model(s) utilized in the NL based control of the computer applications.