Abstract: A system (102) for assisting a patient to raise an alarm is disclosed. The system (102) may include a sensor (106) configured to be positioned at a head region of the patient and to detect movement of head of the patient. The system (102) may further include a patient assisting device (104) coupled to the sensor (106). The patient assisting device (104) may be configured to receive, from the sensor (106), a signal corresponding to the movement of the head of the patient, determine a state of alarm value from the signal, and generate an alarm based on the state of alarm value.

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

Abstract: A method and apparatus for estimating capacity of a system including an energy generation system, an energy storage system or both. The method and apparatus initially estimate the system capacity based on a facility location and size. The initial estimate may be adjusted through adjustment of at least one parameter. An updated capacity estimate is generated and displayed.

Abstract: Example systems and methods provide input suggestions to a user to improve user experience on user devices. The input suggestions can be fill information from another app on device to the present app being used by user, information for performing a search (without the user having to copy-paste data or entering the data manually), responses to a message/notification received by the user, information/content/data to be shared between apps (without switching between apps), and emojis/GIFs that can be used by the user. The method includes analyzing one or more content of one or more screen displayed on device, generating at least one of a logical tree structure and a data mashup model of the one or more analyzed content for each screen, and providing a recommendation to a user. The recommendation can be a connected action or an input suggestion.

Abstract: Systems and methods for enabling access to dedicated resources in a virtual network using top of rack switches are disclosed. A method includes a virtual filtering platform encapsulating at least one packet, received from a virtual machine, to generate at least one encapsulated packet comprising a virtual network identifier (VNI). The method further includes a TOR switch: (1) receiving the at least one encapsulated packet and decapsulating the at least one encapsulated packet to create at least one decapsulated packet, (2) using the VNI to identify a virtual routing and forwarding artifact to determine a virtual local area network interface associated with the dedicated hardware portion, and (3) transmitting the at least one decapsulated packet to the dedicated hardware portion based on at least one policy provided by a controller, where the at least one policy comprises information related to a customer of the service provider.

Abstract: Systems and methods for detecting digital abuse or digital fraud that involves malicious account testing includes implementing a machine learning threat model that predicts malicious account testing using misappropriate accounts, wherein a subset of a plurality of learnable variables of an algorithmic structure of the machine learning threat model includes one or more learnable variables derived based on feature data indicative of malicious account testing; wherein implementing the machine learning threat model includes: (i) identifying event data from an online event that is suspected to involve digital fraud or digital abuse, (ii) extracting adverse feature data from the event data that map to the one or more learnable variables of the subset, and (iii) providing the adverse feature data as model input to the machine learning threat model; and computing, using the machine learning threat model, a threat prediction indicating a probability that the online event involves malicious account testing.

Abstract: Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.

Abstract: Approaches are described for training an action selection neural network system for use in controlling an agent interacting with an environment to perform a task, using a contrastive loss function based on a policy similarity metric. In one aspect, a method includes: obtaining a first observation of a first training environment; obtaining a plurality of second observations of a second training environment; for each second observation, determining a respective policy similarity metric between the second observation and the first observation; processing the first observation and the second observations using the representation neural network to generate a first representation of the first training observation and a respective second representation of each second training observation; and training the representation neural network on a contrastive loss function computed using the policy similarity metrics and the first and second representations.

Abstract: Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer.

Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

Abstract: Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

Abstract: A thermal management system includes a refrigeration circuit that cools at least a first coolant that circulates around a battery cooling loop. Refrigerant of the refrigeration circuit is cooled at a liquid-cooled condenser and at an air-cooled condenser. In certain examples, the liquid-cooled condenser is cooled by coolant circulating along a propeller arrangement cooling loop. In certain examples, the coolant from the propeller arrangement cooling loop may be combined with coolant from the battery cooling loop.

Abstract: A system includes a light source, a first lens, a second lens, a third lens, a beam splitter, a first image collection device, and a second image collection device. The first lens is configured to collimate a light beam and to direct the collimated light beam through a test sample. The beam splitter is configured to split the light beam from the test sample and to transmit a first portion of the light beam toward the second lens and reflect a second portion of the light beam toward the third lens. The first image collection device is positioned adjacent to a first obstruction and configured to record an obstructed first image formed by the first portion of the light beam. The second image collection device is positioned adjacent to a second obstruction and configured to record an obstructed second image formed by the second portion of the light beam.

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

Abstract: Systems and methods are provided for receiving data indicating a spatial distribution and 802.11ax capabilities of access point radios and of client devices in a network, assigning the access point radios as either first access point radios or second access point radios, the first access point radios conducting data transmission using an 802.11ax wireless standard and the second access point radios conducting data transmission using legacy wireless standards, based on the data, determining whether any of the client devices are to be steered to a different access point radio based on the 802.11ax capabilities of the client devices, and in response to determining that a client device is to be steered to a different access point radio, steering the client device to a first access point radio or a second access point radio.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: A thermal management system enables fluid coupling of the cooling circuits for the battery and the propeller arrangements. More than one propeller arrangement can be serviced by the same cooling circuit, but distribution of the coolant may be finessed. Optional pathways are provided to use heated coolant for heating (e.g., de-icing, cabin heating, etc.) before cooling the coolant. Fluid coupling of conduits between and/or within the cooling circuits provide redundancy to accommodate various faults and equipment malfunctions.