Abstract: A method and an apparatus for processing audio commands includes receiving an audio command from a user, determining that a proper response to the audio command is unavailable in a first assistant device based on analyzing the audio command, transmitting the audio command to at least one second assistant device, and receiving at least one response to the audio command from the at least one second assistant device.

Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling an agent interacting with an environment. One of the methods includes obtaining a representation of an observation; processing the representation using a convolutional long short-term memory (LSTM) neural network comprising a plurality of convolutional LSTM neural network layers; processing an action selection input comprising the final LSTM hidden state output for the time step using an action selection neural network that is configured to receive the action selection input and to process the action selection input to generate an action selection output that defines an action to be performed by the agent at the time step; selecting, from the action selection output, the action to be performed by the agent at the time step in accordance with an action selection policy; and causing the agent to perform the selected action.

Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first conductive layer over a substrate, a first transistor having first interconnects in the first conductive layer, and a second conductive layer on an insulating layer that is on the first conductive layer. The transistor device also includes a second transistor having second interconnects in the second conductive layer, and a gate electrode over the substrate, where the gate electrode has a workfunction metal that surrounds the first and second interconnects. The first and second conductive layers may include conductive materials such as an epitaxial (EPI) layer, a metal layer, or a doped-semiconductor layer. The transistor device may further include a dielectric surrounding the interconnects as the dielectric is surrounded with the workfunction metal, and a transition layer disposed between the dielectric and interconnects. The dielectric may include a high-k dielectric material.

Abstract: Integrated circuit structures having asymmetric source and drain structures, and methods of fabricating integrated circuit structures having asymmetric source and drain structures, are described. For example, an integrated circuit structure includes a fin, and a gate stack over the fin. A first epitaxial source or drain structure is in a first trench in the fin at a first side of the gate stack. A second epitaxial source or drain structure is in a second trench in the fin at a second side of the gate stack, the second epitaxial source or drain structure deeper into the fin than the first epitaxial source or drain structure.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: An apparatus includes a switch having alternately open and closed conditions, and a shunt trip mechanism configured to detect and respond to an electrical fault condition. The apparatus further includes an operating mechanism including a spring assembly. The operating mechanism is actuatable manually to deflect the spring assembly into a stressed condition, and is actuatable automatically in response to the shunt trip mechanism to shift the switch into the open condition upon return deflection of the spring assembly from the stressed condition. The spring assembly may include springs connected in parallel.

Abstract: A system and method is provided for providing a cosmetic composition to a user. The system includes an apparatus configured to dispense at least one cosmetic composition into a output container; a user interface configured to receive information about the user; and circuitry configured to receive the information about the user and determine one or more cosmetic compositions to be dispensed into the output container based on the information about the user received at the user interface.

Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

Abstract: A virtual network interface controller (NIC) associated with a virtual machine in a cloud computing network is configured to support one or more network containers that encapsulate networking configuration data and policies that are applicable to a specific discrete computing workload to thereby enable the virtual machine to simultaneously belong to multiple virtual networks using the single NIC. The network containers supported by the NIC can be associated with a single tenant to enable additional flexibility such quickly switching between virtual networks and support pre-provisioning of additional computing resources with associated networking policies for rapid deployment. The network containers can also be respectively associated with different tenants so that the single NIC can support multi-tenant services on the same virtual machine.

Abstract: Improved sensor assemblies are provided. More particularly, the present disclosure provides improved and highly advantageous metal oxide based sensor assemblies configured to sense low concentration of specific gases, and related methods of use. The present disclosure provides improved physical forms of metal oxide films (e.g., WOx films, CeOx films). The exemplary metal oxide films can be fabricated by a Reactive Spray Deposition Technology (RSDT). The highly advantageous films/materials can be utilized in sensor assemblies to detect simple chemical components of the breath that correlate with human health conditions (e.g., the presence of acetone in diabetic patients). These films/materials demonstrate improved thermal stability under the sensor's operating conditions, as well as improved sensitivity to low concentration of the analyte, selectivity and quick responsiveness.

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

Abstract: The techniques described herein enable a private connectivity solution between a virtual network of a service consumer and a virtual network of a service provider in a cloud-based platform. The techniques map a service (e.g., one or more workloads or containers) executing in the virtual network of the service provider into the virtual network of the service consumer. The mapping uses network address translation (NAT) that is performed by the cloud-based infrastructure. As a result of the techniques described herein, a public Internet Protocol (IP) address does not need to be used to establish a connection thereby alleviating privacy and/or security concerns for the virtual networks of the service provider and/or the service consumer that are hosted by the cloud-based platform.

Abstract: An apparatus is provided for dispensing a cosmetic composition, including: a cartridge holder configured to hold at least one cartridge that stores a cosmetic composition, the cartridge holder being configured to move the cartridge to a predetermined location; a container receiving area configured to hold a output container beneath the predetermined location; circuitry configured to determine the cosmetic composition in the cartridge holder, control the cartridge holder to move the cartridge holder to the predetermined location based on the determination, and control the cartridge to dispense the cosmetic composition into the output container; and a mixer configured to hold the output container and subject the output container to a predetermined movement to cause contents of the output container to mix together.

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

Abstract: Techniques are disclosed which provide for transforming a hierarchical table to a relational table. A hierarchical table may be received, in which a headline row is identified. A candidate row may be determined in the hierarchical table. The process may include systematically classifying headlines as data headlines or descriptors. For each data headline a new column may be generated, while for each descriptor headline, the table may be split to produce a resultant table. The resultant table may be stored and the process may be repeated until there are no headlines left to be classified. The steps performed by the system to transform the table can then be displayed on a user device using a program in the Domain-specific language, which can then be further inspected or modified to perform the desired table transformation.

Abstract: Techniques are provided for improving the performance of a constellation of coprocessors by hardware support for asynchronous events. In an embodiment, a coprocessor receives an event descriptor that identifies an event and a logic. The coprocessor processes the event descriptor to configure the coprocessor to detect whether the event has been received. Eventually a device, such as a CPU or another coprocessor, sends the event. The coprocessor detects that it has received the event. In response to detecting the event, the coprocessor performs the logic.

Abstract: Methods, systems, and computer program products for automatically suggesting a temporal opportunity for writing one or more sequel articles via artificial intelligence are provided herein. A computer-implemented method includes extracting one or more types of information from a prior written document; automatically determining, based on the extracted information, at least one temporal opportunity for generating a follow-up written document to the prior written document; automatically generating a follow-up written document to the prior written document, the follow-up written document being written in a style that indicates that it is in response to the prior written document, in accordance with the at least one determined temporal opportunity, and based on (i) one or more items of information, related to the extracted information, derived from one or more web sources, and (ii) a writing model attributed to a user.