Patents by Inventor Rishabh

Rishabh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10740390
    Abstract: An embodiment may involve a server device transmitting, over a wide area network, a first playlist with a first duration to a client device. Possibly while the client device is playing out a current audio file of a first plurality of audio files in the playlist, the server device may receive an instruction from the client device and generate a second playlist. The second playlist may include references to a second plurality of audio files, where playout of the second plurality of audio files may have a duration that is less than the duration of the playout of the first plurality of audio files. The server device may transmit, over the wide area network, the second playlist to the client device. Reception of the second playlist at the client device may cause the audio player application to retrieve and play out the second plurality of audio files.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 11, 2020
    Assignee: Gracenote, Inc.
    Inventors: Rishabh Sharma, Markus Cremer
  • Patent number: 10742501
    Abstract: An example method includes determining, by a network controller, based on a high-level data model, vendor-agnostic device information for a first network device, translating the vendor-agnostic device information into vendor-specific device information, sending, to the first network device, first configuration information included in the vendor-specific device information to cause the first network device to switch into a maintenance mode and enable diversion of network traffic from the first network device to a second network device, responsive to verifying that the first network device has diverted the traffic, initiating maintenance procedures on the first network device while the first network device is in the maintenance mode, and sending, to the first network device, second configuration information included in the vendor-specific device information to cause the first network device to switch out of the maintenance mode and enable reversion of network traffic from the second device to the first network
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Jacopo Pianigiani, Michal Styszynski, Atul S Moghe, Joseph Williams, Sahana Sekhar Palagrahara Chandrashekar, Tong Jiang, Rishabh Ramakant Tulsian, Manish Krishnan, Soumil Ramesh Kulkarni, Vinod Nair, Jeba Paulaiyan, Sukhdev S. Kapur, Ashok Ganesan
  • Publication number: 20200251402
    Abstract: A thermal conducting sheet, including: a binder resin; insulating-coated carbon fibers; and a thermal conducting filler other than the insulating-coated carbon fibers, wherein a mass ratio (insulating-coated carbon fibers/binder resin) of the insulating-coated carbon fibers to the binder resin is less than 1.30, and wherein the insulating-coated carbon fibers include carbon fibers and a coating film over at least a part of a surface of the carbon fibers, the coating film being formed of a cured product of a polymerizable material.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Hiroki Kanaya, Shinichi Uchida, Shunsuke Uchida, Gupta Rishabh, Keisuke Aramaki
  • Publication number: 20200251502
    Abstract: An apparatus includes a first layer, a second layer under the first layer along an axis, and a metal layer between the first layer and the second layer along the axis. The first layer includes a first plurality of transistors, where a given transistor of the first plurality of transistors includes a gate region; and the second layer includes a second plurality of transistors. The metal layer includes a metal below the gate region, and the metal is within thirty nanometers (nm) of the gate region.
    Type: Application
    Filed: December 26, 2017
    Publication date: August 6, 2020
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady
  • Patent number: 10732865
    Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: August 4, 2020
    Assignee: Oracle International Corporation
    Inventors: Rishabh Jain, Erik M. Schlanger
  • Patent number: 10734305
    Abstract: A thermal conducting sheet, including: a binder resin; insulating-coated carbon fibers; and a thermal conducting filler other than the insulating-coated carbon fibers, wherein a mass ratio (insulating-coated carbon fibers/binder resin) of the insulating-coated carbon fibers to the binder resin is less than 1.30, and wherein the insulating-coated carbon fibers include carbon fibers and a coating film over at least a part of a surface of the carbon fibers, the coating film being formed of a cured product of a polymerizable material.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 4, 2020
    Assignee: DEXERIALS CORPORATION
    Inventors: Hiroki Kanaya, Shinichi Uchida, Shunsuke Uchida, Gupta Rishabh, Keisuke Aramaki
  • Patent number: 10728090
    Abstract: Examples of systems described herein include a file server virtual machine of a virtualized file server configured to communicate with a user virtual machine over a first virtual network to transfer data and to communicate with a controller virtual machine over a second virtual network to transfer control information.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 28, 2020
    Assignee: Nutanix, Inc.
    Inventors: Satyajit Sanjeev Deshmukh, Devyani Suryakant Kanada, Anil Kumar Gopalapura Venkatesh, Kalpesh Ashok Bafna, Rishabh Sharma, Mausumi Ranasingh, Simon Martin Mijolovic
  • Patent number: 10725947
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 28, 2020
    Assignee: Oracle International Corporation
    Inventors: Rishabh Jain, David A. Brown, Michael Duller, Christopher Joseph Daniels, Erik M. Schlanger
  • Publication number: 20200235013
    Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.
    Type: Application
    Filed: August 24, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Aaron Lilak, Sean Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow, Patrick H. Keys
  • Publication number: 20200234145
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for selecting actions to be performed by an agent interacting with an environment. In one aspect, a method comprises: obtaining a graph of nodes and edges that represents an interaction history of the agent with the environment; generating an encoded representation of the graph representing the interaction history of the agent with the environment; processing an input based on the encoded representation of the graph using an action selection neural network, in accordance with current values of action selection neural network parameters, to generate an action selection output; and selecting an action from a plurality of possible actions to be performed by the agent using the action selection output generated by the action selection neural network.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 23, 2020
    Inventors: Hanjun Dai, Yujia Li, Chenglong Wang, Rishabh Singh, Po-Sen Huang, Pushmeet Kohli
  • Publication number: 20200235134
    Abstract: Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady, Anh Phan
  • Publication number: 20200235092
    Abstract: An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Aaron D. Lilak, Cheng-ying Huang, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru
  • Patent number: 10719306
    Abstract: Particular embodiments provide a plurality of host machines, one or more virtual disks comprising a plurality of storage devices, and a virtualized file server (VFS) comprising a plurality of file server virtual machines (FSVMs), wherein each of the FSVMs is running on one of the host machines and conducts I/O transactions with the one or more virtual disks. A distributed health monitoring service (HMS) may be running on each of the host machines running a FSVM. The HMS may monitor the FSVMs to determine whether any of the FSVMs has failed or is having problems. The HMS may detect that a plurality of the FSVMs have failed, wherein the failed FSVMs form a portion of the FSVMs comprising the VFS. For each of the failed FSVMs, the HMS may reassign an IP address corresponding to the failed FSVM to a live one of the FSVMs.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 21, 2020
    Assignee: Nutanix, Inc.
    Inventors: Satyajit Sanjeev Deshmukh, Richard James Sharpe, Durga Mahesh Arikatla, Shyamsunder Prayagchand Rathi, Rishabh Sharma
  • Publication number: 20200227558
    Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Applicant: INTEL CORPORATION
    Inventors: Rishabh Mehandru, Anand Murthy, Karthik Jambunathan, Cory Bomberger
  • Publication number: 20200227556
    Abstract: Techniques and mechanisms for imposing stress on transistors using an insulator. In an embodiment, an integrated circuit device includes a fin structure on a semiconductor substrate, wherein respective structures of two transistors are variously in or on the fin structure. A recess of the IC device, located in a region between the two transistors, extends at least partially through the fin structure. An insulator in the recess imposes stresses on respective channel regions of the two transistors. In another embodiment, compressive stresses or tensile stresses are imposed on the transistors with both the insulator and a buffer layer under the fin structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Applicant: INTEL CORPORATION
    Inventor: Rishabh Mehandru
  • Patent number: 10713429
    Abstract: Provided are methods and systems for joining semi-structured data from the web with relational data in a spreadsheet table using input-output examples. A first sub-task performed by the system learns a string transformation program to transform input rows of a table to URL strings that correspond to the webpages where the relevant data is present. A second sub-task learns a program in a rich web data extraction language to extract desired data from the webpage given the example extractions. Hierarchical search and input-driven ranking are used to efficiently learn the programs using few input-output examples. The learnt programs are then run on the remaining spreadsheet entries to join desired data from the corresponding web pages.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 14, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Rishabh Singh, Jeevana Priya Inala
  • Patent number: 10710806
    Abstract: Disclosed are various embodiments that may facilitate transferring an item to a receptacle using a conveyor and a robotic drive unit. The robotic drive unit moves to be proximate to a receptacle. The robotic drive unit can align an item with the receptacle. The item can be transferred to the receptacle via the conveyor.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 14, 2020
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Rishabh Agarwal, Venkataramanan Subramanian, Mustafa Mustansir Hussain, Ahmed Shareef, Vikas Vishwanatham
  • Publication number: 20200218558
    Abstract: A method to provide network connectivity to a virtual machine hosted on a server computer system includes detecting a change in a configuration of a software-defined network to which the server computer system provides access; issuing a network configuration update (NCU) for consumption by the virtual machine, the NCU including a data structure reflecting the change in the configuration; and providing a link-state notification (LSN) to a virtual network interface card of the virtual machine pursuant to the change in the configuration, the LSN including data indicating a state of network connectivity of the virtual machine. Receipt of the LSN triggers a dynamic host-configuration protocol (DHCP) handshake by the virtual machine; the NCU is received by the virtual machine pursuant to the DHCP handshake.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 9, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Abhishek ELLORE SREENATH, Madhan SIVAKUMAR, Abhishek SHUKLA, Rishabh TEWARI
  • Publication number: 20200219997
    Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA, Biswajeet GUHA
  • Publication number: 20200218576
    Abstract: Systems and methods may use models to generate predictions of specific access rights for users. Further, systems and methods may generate the predictions in an environment in which the availability of the specific access rights change frequently. The access rights, predicted using embodiments described herein, may be both available and associated with user affinities. An interface associated with the primary load management system may be configured to display the predicted access rights for a user operating a user device.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 9, 2020
    Inventors: Ish Rishabh, Mark Roden, Chris Smith, Spencer Brown, Scott Kline, Krisha Zagura