Patents by Inventor Rishikesh Krishnan
Rishikesh Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8861179Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: August 29, 2012Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8809176Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.Type: GrantFiled: March 15, 2013Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Takashi Ando, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
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Publication number: 20140183051Abstract: A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Min Dai, Rishikesh Krishnan, Joseph F. Shepard, JR.
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Patent number: 8679938Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.Type: GrantFiled: February 6, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Sunfei Fang, Oleg Gluschenkov, Byeong Y. Kim, Rishikesh Krishnan, Daewon Yang
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Patent number: 8673390Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.Type: GrantFiled: September 13, 2012Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Rishikesh Krishnan, Daniel F. Gealy
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Publication number: 20140057426Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.Type: ApplicationFiled: October 29, 2013Publication date: February 27, 2014Applicant: International Business Machines CorporationInventors: Nicolas Breil, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon
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Patent number: 8592325Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.Type: GrantFiled: January 11, 2010Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Joseph F. Shepard, Jr., Siddarth A. Krishnan, Rishikesh Krishnan, Michael P. Chudzik
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Patent number: 8581351Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.Type: GrantFiled: January 14, 2011Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Takashi Ando, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
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Publication number: 20130258550Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.Type: ApplicationFiled: May 28, 2013Publication date: October 3, 2013Inventors: Rishikesh Krishnan, F. Daniel Gealy, Vidya Srividya, Noel Rocklein
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Publication number: 20130200482Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: International Business Machines CorporationInventors: Sunfei FANG, Oleg GLUSCHENKOV, Byeong Y. KIM, Rishikesh KRISHNAN, Daewon YANG
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Publication number: 20130175665Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
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Patent number: 8450173Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.Type: GrantFiled: June 28, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, Daniel Gealy, Vidya Srividya, Noel Rocklein
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Publication number: 20130105879Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.Type: ApplicationFiled: December 15, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicolas Breil, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon
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Publication number: 20130011990Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishwanath Bhat, Rishikesh Krishnan, Daniel Gealy
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Publication number: 20120320494Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: ApplicationFiled: August 29, 2012Publication date: December 20, 2012Applicant: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8310807Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: June 12, 2009Date of Patent: November 13, 2012Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Publication number: 20120282754Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8282988Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.Type: GrantFiled: August 16, 2011Date of Patent: October 9, 2012Assignee: Micron Technology, IncInventors: Vishwanath Bhat, Rishikesh Krishnan, Daniel F. Gealy
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Patent number: 8241981Abstract: A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.Type: GrantFiled: January 31, 2011Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Rishikesh Krishnan, Joseph F. Shepard, Jr., Michael P. Chudzik, Christian Lavoie, Dong-Ick Lee, Oh-Jung Kwon, Unoh Kwon, Youngjin Choi
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Patent number: 8236372Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: June 12, 2009Date of Patent: August 7, 2012Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hall, Chris Carlson