Patents by Inventor Roawen Chen
Roawen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9768144Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.Type: GrantFiled: February 5, 2016Date of Patent: September 19, 2017Assignee: Marvell World Trade Ltd.Inventors: Albert Wu, Roawen Chen, Chung Chyung (Justin) Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Patent number: 9478541Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.Type: GrantFiled: September 8, 2014Date of Patent: October 25, 2016Assignee: QUALCOMM INCORPORATEDInventors: Stanley Seungchul Song, Kern Rim, Jeffrey Junhao Xu, Matthew Michael Nowak, Choh Fei Yeap, Roawen Chen
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Patent number: 9391045Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.Type: GrantFiled: May 18, 2015Date of Patent: July 12, 2016Assignee: Marvell World Trade Ltd.Inventors: Albert Wu, Roawen Chen, Chung Chyung (Justin) Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20160155732Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 5, 2016Publication date: June 2, 2016Inventors: Albert Wu, Roawen Chen, Chung Chyung (Justin) Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20160071847Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Inventors: Stanley Seungchul SONG, Kern RIM, Jeffrey Junhao XU, Matthew Michael NOWAK, Choh Fei YEAP, Roawen CHEN
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Patent number: 9257410Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.Type: GrantFiled: January 24, 2011Date of Patent: February 9, 2016Assignee: Marvell World Trade Ltd.Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20150279806Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 18, 2015Publication date: October 1, 2015Inventors: Albert Wu, Roawen Chen, Chung Chyung (Justin) Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Patent number: 9034730Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.Type: GrantFiled: January 28, 2011Date of Patent: May 19, 2015Assignee: Marvell World Trade Ltd.Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Patent number: 8935464Abstract: A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-state memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.Type: GrantFiled: April 30, 2014Date of Patent: January 13, 2015Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Po-Chien Chang, Roawen Chen
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Publication number: 20140306349Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: QUALCOMM IncorporatedInventors: Shiqun Gu, Urmi Ray, Roawen Chen, Brian Matthew Henderson, Ratibor Radojcic, Matthew Nowak, Nicholas Yu
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Publication number: 20140237171Abstract: A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-sate memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicant: Marvell World Trade LTD.Inventors: Sehat Sutardja, Po-Chien Chang, Roawen Chen
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Publication number: 20140124961Abstract: Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Marvell World Trade Ltd.Inventors: Albert WU, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Patent number: 8719485Abstract: A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network.Type: GrantFiled: March 11, 2009Date of Patent: May 6, 2014Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Po-Chien Chang, Roawen Chen
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Patent number: 8008137Abstract: An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.Type: GrantFiled: February 12, 2007Date of Patent: August 30, 2011Assignee: Marvell World Trade Ltd.Inventors: Albert Wu, Roawen Chen
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Publication number: 20110186998Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 24, 2011Publication date: August 4, 2011Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20110186960Abstract: Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 14, 2011Publication date: August 4, 2011Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20110186992Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 28, 2011Publication date: August 4, 2011Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Patent number: 7820493Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.Type: GrantFiled: February 4, 2008Date of Patent: October 26, 2010Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
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Patent number: 7704805Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.Type: GrantFiled: February 4, 2008Date of Patent: April 27, 2010Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
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Publication number: 20090327588Abstract: A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network.Type: ApplicationFiled: March 11, 2009Publication date: December 31, 2009Inventors: Sehat Sutardja, Po-Chien Chang, Roawen Chen