TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

Abstract

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This disclosure claims priority to U.S. Provisional Patent Application No. 61/301,125, filed Feb. 3, 2010, and to U.S. Provisional Patent Application No. 61/316,282, filed Mar. 22, 2010, and to U.S. Provisional Patent Application No. 61/321,068, filed Apr. 5, 2010, and to U.S. Provisional Patent Application No. 61/325,189, filed Apr. 16, 2010, the entire specifications of which are hereby incorporated by reference in their entirety for all purposes, except for those sections, if any, that are inconsistent with this specification.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly, to techniques, structures, and configurations of recessed semiconductor substrates for package assemblies.

BACKGROUND

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Integrated circuit devices, such as transistors, are formed on dies or chips that continue to scale in size to smaller dimensions. The shrinking dimensions of the dies are challenging conventional substrate fabrication and/or package assembly technologies that are currently used to route electrical signals to or from the semiconductor die. For example, laminate substrate technologies may not produce sufficiently small features on a substrate to correspond with the finer pitches of interconnects or other signal-routing features formed on the dies.

SUMMARY

In one embodiment, the present disclosure provides a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies.

In another embodiment, the present disclosure provides an apparatus comprising a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, a dielectric film formed on the first surface of the semiconductor substrate, a redistribution layer formed on the dielectric film, one or more dies electrically coupled to the redistribution layer, a molding compound formed on the semiconductor substrate, one or more channels formed through the second surface of the semiconductor substrate, and one or more package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 schematically illustrates a package assembly that includes a recessed semiconductor substrate.

FIGS. 2A-2I schematically illustrate a package assembly subsequent to various process operations.

FIG. 3 schematically illustrates another package assembly that includes a recessed semiconductor substrate.

FIG. 4 is a process flow diagram of a method to fabricate a package assembly described herein.

DETAILED DESCRIPTION

Embodiments of the present disclosure describe techniques, structures, and configurations for a semiconductor substrate having a recessed region and associated package assemblies. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout. Other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

The description may use perspective-based descriptions such as up/down, over/under, and/or top/bottom. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

For the purposes of the present disclosure, the phrase “A/B” means A or B. For the purposes of the present disclosure, the phrase “A and/or B” means “(A), (B), or (A and B).” For the purposes of the present disclosure, the phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).” For the purposes of the present disclosure, the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

The description uses the phrases “in an embodiment,” “in embodiments,” or similar language, which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

FIG. 1 schematically illustrates a package assembly 100 that includes a recessed semiconductor substrate 102. The package assembly 100 generally includes a semiconductor substrate 102, which is a substrate or interposer that substantially comprises a semiconductor material such as, for example, silicon (Si). That is, the bulk of the material of the semiconductor substrate 102 is a semiconductor material. The semiconductor material can include crystalline and/or amorphous types of material. In the case of silicon, for example, the silicon can include single crystal and/or polysilicon types. In other embodiments, the semiconductor substrate 102 can include other semiconductor materials such as, for example, germanium, group III-V materials, or group II-VI materials, that may also benefit from the principles described herein.

The semiconductor substrate 102 includes a first surface, A1, and a second surface, A2, that is disposed opposite to the first surface A1. The first surface A1 and the second surface A2 generally refer to opposing surfaces of the semiconductor substrate 102 to facilitate the description of various configurations described herein.

According to various embodiments, a portion of the second surface A2 is recessed to provide a thickness, T, that facilitates the formation of one or more channels 104 through the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 is recessed to have a thickness T between about 10 microns and about 500 microns. The thickness is not limited to this range and other thicknesses, both greater and smaller, can be used in other embodiments.

The semiconductor substrate 102 is fabricated using technologies similar to those that are generally known to fabricate integrated circuit (IC) structures on a die or chip. For example, well-known patterning processes such as lithography/etch and/or deposition processes for fabricating IC devices on a die can be used to form features of the semiconductor substrate 102. By using semiconductor fabrication techniques, the semiconductor substrate 102 can include smaller features than other types of substrates such as laminate (e.g., organic) substrates. The semiconductor substrate 102 facilitates routing of electrical signals, such as input/output (I/O) and/or power/ground signals, for dies, which continue to shrink in size. For example, in some embodiments, the semiconductor substrate 102 allows for fine pitch Si-to-Si interconnects and final line routing between the semiconductor substrate 102 and one or more dies 108.

A dielectric film 105 is formed on the first surface A1 and/or the second surface A2 of the semiconductor substrate. The dielectric film 105 can include, for example, silicon dioxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiO_xN_y), where x and y represent suitable stoichiometric values, or other suitable dielectric materials. The dielectric film 105 generally provides electrical isolation for electrically conductive material disposed on the semiconductor substrate to prevent current leakage between the electrically conductive material and the semiconductor material (e.g., silicon) of the semiconductor substrate.

One or more redistribution layers 106 are formed on the dielectric film 105 to route the electrical signals of the one or more dies 108 that are coupled to the semiconductor substrate 102. For example, the one or more redistribution layers 106 can provide electrical routing between the one or more dies 108 and one or more package interconnect structures 114 disposed in the one or more channels 104.

The one or more redistribution layers 106 generally include an electrically conductive material such as, for example, a metal (e.g., copper or aluminum). Other suitable electrically conductive materials can be used to form the one or more redistribution layers 106 in other embodiments.

The one or more redistribution layers 106 can include a variety of structures to route the electrical signals such as, for example, pads, lands, or traces. Although not depicted, a passivation layer comprising an electrically insulative material such as polyimide, for example, can be deposited on the one or more redistribution layers 106 and patterned to provide openings in the passivation layer to allow electrical coupling of the one or more dies 108 to the one or more redistribution layers 106.

One or more dies 108 are coupled to the semiconductor substrate 102. The one or more dies 108 generally comprise a semiconductor material, such as, for example, silicon. In an embodiment, the one or more dies 108 and the semiconductor substrate 102 are fabricated using the same semiconductor material to reduce stress associated with heating/cooling mismatch of materials such as, for example, mismatched coefficients of thermal expansion (CTE).

The one or more dies 108 can be coupled to the semiconductor substrate 102 using any suitable configuration. The one or more dies 108 generally have an active side that includes a surface upon which a plurality of integrated circuit (IC) devices (not shown) such as transistors for logic and/or memory are formed and an inactive side that is disposed opposite to the active side. The active side of the one or more dies 108 is electrically coupled to the one or more redistribution layers 106.

In some embodiments, the active side of the one or more dies 108 is coupled to the one or more redistribution layers 106 using one or more bumps 110 in a flip-chip configuration, as can be seen. In other embodiments, the active side of the one or more dies 108 is electrically coupled to the one or more redistribution layers 106 using other structures, such as, for example, one or more bonding wires to provide a wire-bonding configuration.

The one or more bumps 110 generally comprise an electrically conductive material such as, for example, solder or other metal to route the electrical signals of the one or more dies 108. According to various embodiments, the one or more bumps 110 comprise lead, gold, tin, copper, or lead-free materials, or combinations thereof. The one or more bumps 110 can have a variety of shapes including spherical, cylindrical, rectangular, or other shapes and can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable process.

Although not shown, one or more other active or passive components can be mounted on the semiconductor substrate 102. The components can include Electronic Compounds and integrated circuits (ICs). The components can include, for example, filter components, resistors, inductors, power amplifiers, capacitors, or packaged ICs. Other active or passive components can be coupled to the semiconductor substrate 102 in other embodiments.

A molding compound 112 is disposed on the first surface A1 of the semiconductor substrate 102. The molding compound 112 generally comprises an electrically insulative material, such as a thermosetting resin, that is disposed to protect the one or more dies 108 from moisture, oxidation, or chipping associated with handling. In some embodiments, the molding compound 112 is disposed to substantially encapsulate the one or more dies 108 and substantially fill a region between the one or more dies 108 and the semiconductor substrate 102 (e.g., between the one or more bumps 110), as can be seen. The molding compound 112 can be selected to have a coefficient of thermal expansion (CTE) that is substantially the same or similar to a CTE of the semiconductor substrate 102 and/or the one or more dies 108 to reduce stress associated with mismatched CTE materials.

According to various embodiments, one or more channels 104, which may also be referred to as vias, are formed through the recessed surface (e.g., the second surface A2) of the semiconductor substrate 102. The one or more channels 104 are filled with an electrically conductive and/or thermally conductive material such as a metal used to form one or more package interconnect structures 114. The one or more channels 104 generally provide an electrical and/or thermal pathway between the first surface A1 and the second surface A2 of the semiconductor substrate 102. In an embodiment where the semiconductor substrate 102 comprises silicon, the one or more channels 104 are one or more through-silicon vias (TSVs). In some embodiments, the one or more channels 104 are tapered. The one or more channels 104 can be straight or have other shapes in other embodiments.

One or more package interconnect structures 114 such as, for example, one or more solder balls or posts are disposed in the one or more channels 104 to further route the electrical signals of the one or more dies 108. The one or more package interconnect structures 114 are electrically coupled to the one or more redistribution layers 106 through the one or more channels 104. In the depicted embodiment of FIG. 1, the one or more package interconnect structures 114 are directly coupled to the one or more redistribution layers 106 formed on the first surface A1 of the semiconductor substrate 102.

The one or more package interconnect structures 114 generally comprise an electrically conductive material such as a metal. The one or more package interconnect structures 114 can be formed in a variety of shapes including spherical, planar, or polygon shapes and can be positioned in a variety of positions including in a row or in an array of multiple rows. Although the one or more package interconnect structures 114 are depicted on a peripheral portion of the semiconductor substrate 102, the one or more package interconnect structures 114 can be disposed on or near a central portion of the semiconductor substrate 102 in other embodiments.

The package assembly 100 can be electrically coupled to another electronic device 150 using the one or more package interconnect structures 114 to further route the electrical signals of the one or more dies 108 to the other electronic device 150. The other electronic device 150 can include, for example, as a printed circuit board (PCB) (e.g., motherboard), a module, or another package assembly.

FIGS. 2A-2I schematically illustrate a package assembly subsequent to various process operations. Referring to FIG. 2A, a package assembly 200 is depicted subsequent to forming a dielectric film 105 on at least the first surface A1 of the semiconductor substrate 102. In embodiments, the dielectric film 105 is formed on the first surface A1 and the second surface A2 of the semiconductor substrate 102, as can be seen. The dielectric film 105 can be formed by using a deposition technique such as, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD) to deposit a dielectric material such as, for example, silicon dioxide (SiO₂), silicon nitride (SiN), or silicon oxynitride (SiO_xN_y). Other suitable deposition techniques and/or dielectric materials can be used in other embodiments.

Referring to FIG. 2B, the package assembly 200 is depicted subsequent to forming one or more redistribution layers 106 on the dielectric film 105 that is disposed on the first surface A1. The one or more redistribution layers 106 are generally formed by depositing an electrically conductive material on the dielectric film 105. The deposited electrically conductive material can be patterned and/or etched to provide routing structures (e.g., traces or pads) that route electrical signals of one or more dies (e.g., the one or more dies 108 of FIG. 2C). Multiple redistribution layers can be stacked on the semiconductor substrate 102 to provide desired routing of the electrical signals.

Referring to FIG. 2C, the package assembly 200 is depicted subsequent to electrically coupling one or more dies 108 to the one or more redistribution layers 106. The one or more dies 108 can be coupled to the semiconductor substrate 102 in a variety of configurations including, for example, flip-chip or wire-bonding configurations, or combinations thereof. In a flip-chip configuration, an active surface of the die is coupled to the one or more redistribution layers 106 using one or more bumps 110. In a wire-bonding configuration, an inactive surface of the die is coupled to the semiconductor substrate 102 using an adhesive and an active surface of the die is electrically coupled to the one or more redistribution layers 106 using one or more bonding wires.

In the depicted embodiment of FIG. 2C, one or more bumps 110 are formed on the one or more dies 108 and bonded to the one or more redistribution layers 106 in a flip-chip configuration. The one or more bumps 110 can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable process. The one or more bumps 110 can be formed on the one or more dies 108 when the one or more dies 108 are in either wafer or singulated form. The one or more dies 108 can be attached to the semiconductor substrate 102 when the semiconductor substrate 102 is in either wafer or singulated form.

Referring to FIG. 2D, the package assembly 200 is depicted subsequent to forming a molding compound 112 on the semiconductor substrate 102. The molding compound 112 is generally formed by depositing an electrically insulative material to encapsulate the one or more dies 108. According to various embodiments, the molding compound 112 is formed by depositing a resin (e.g., a thermosetting resin) in solid form (e.g., a powder) into a mold and applying heat and/or pressure to fuse the resin. Other well-known techniques for forming the molding compound 112 can be used in other embodiments.

The molding compound 112 can be used in conjunction with an underfill layer (e.g., underfill 118 of FIG. 3), in some embodiments. For example, underfill material may be disposed between the one or more dies 108 and the semiconductor substrate 102 to encapsulate the one or more bumps 110 and the molding compound 112 can be disposed to encapsulate the one or more dies 108 and the underfill. In some embodiments, the molding compound 112 can be formed such that a surface of the one or more dies 108 is exposed to facilitate heat dissipation from the one or more dies 108.

Referring to FIG. 2E, the package assembly 200 is depicted subsequent to recessing the second surface A2 of the semiconductor substrate 102. The semiconductor substrate 102 can be recessed by a grinding process or an etch process to provide a semiconductor substrate 102 having a thickness between about 10 microns and about 500 microns. Other recessing techniques and thicknesses can be used in other embodiments. The semiconductor substrate 102 is recessed to provide a thinner substrate that facilitates or enables the formation of one or more channels (e.g., one or more channels 104) that pass completely through the semiconductor substrate 102. According to various embodiments, the molding compound 112 is used as a mechanical carrier to support the semiconductor substrate 102 when the second surface A2 of the semiconductor substrate 102 is being recessed and/or when the actions described in connection with FIGS. 2H and 2I are performed.

Referring to FIG. 2F, the package assembly 200 is depicted subsequent to forming one or more channels 104 through the semiconductor substrate 102. The one or more channels 104 are formed in/through the second surface A2 of the semiconductor substrate 102 to expose the dielectric film 105, as can be seen. The one or more channels 104 can be formed by selectively removing the semiconductor material of the semiconductor substrate 102. For example, the second surface A2 of the semiconductor substrate can be patterned with a photoresist film or hard mask and etched by wet or dry etching processes to remove the semiconductor material from selected locations, as patterned. In some embodiments, the etch process is a selective etch and the dielectric film 105 serves as an etch stop layer. According to various embodiments, the one or more channels 104 are formed subsequent to the molding compound 112 being formed.

Referring to FIG. 2G, the package assembly 200 is depicted subsequent to removing portions of the dielectric film 105 exposed in the one or more channels 104 in order to expose the one or more redistribution layers 106. Dielectric material of the dielectric film 105 can be selectively removed using, for example, a wet or dry patterning/etching process or a laser drilling process. The electrically conductive material of the one or more redistribution layers 106 can serve as an etch/laser stop material.

Referring to FIG. 2H, the package assembly 200 is depicted subsequent to forming one or more under-ball metallization (UBM) structures 116 in the one or more channels 104. The one or more UBM structures 116 are generally formed by depositing an electrically conductive material using any suitable deposition process. The one or more UBM structures 116 may serve as a buffer between material of the one or more package interconnect structures (e.g., the one or more package interconnect structures 114 of FIG. 2I) and semiconductor material of the semiconductor substrate 102. In some embodiments, the one or more UBM structures 116 are formed on the exposed portions of the one or more redistribution layers 106 in the one or more channels 104 and formed on the semiconductor substrate 102 within the one or more channels 104. In other embodiments, the one or more UBM structures 116 are not formed at all (e.g., as can be seen in the package assembly 100 of FIG. 1). Forming the UBM structures 116 may provide increased joint reliability. Not forming the UBM structures 116 may simplify the fabrication process and/or reduce costs associated with the fabrication process.

Referring to FIG. 2I, the package assembly 200 is depicted subsequent to forming one or more package interconnect structures 114 in the one or more channels 104. The one or more package interconnect structures 114 are electrically coupled to the one or more redistribution layers 106 to route the electrical signals of the one or more dies 108. In some embodiments, the one or more package interconnect structures 114 are formed on the one or more UBM structures 116. In other embodiments, the one or more package interconnect structures 114 are formed directly on the one or more redistribution layers 106.

The one or more package interconnect structures 114 can be formed according to a variety of suitable techniques including, for example, screen printing, electrical plating, and/or solder ball placement. The one or more package interconnect structures 114 can be configured in a variety of ways including, for example, a ball-grid array (BGA) configuration.

FIG. 3 schematically illustrates another package assembly 300 that includes a recessed semiconductor substrate 102. The package assembly 300 is similar to the package assembly 200 depicted in FIG. 2I, except that the package assembly 300 further includes (i) an underfill 118 disposed between the one or more dies 108 and the semiconductor substrate 102 and (ii) an exposed backside surface of the one or more dies 108.

The underfill 118 can be formed, for example, prior to forming the molding compound 112 (e.g., as shown in the package assembly 200 of FIG. 2C). According to various embodiments, the underfill 118 is deposited in liquid form by a liquid dispensing or injection process. The underfill 118 can include, for example, an epoxy or other suitable electrically insulative material. The underfill 118 generally increases adhesion between the one or more dies 108 and the semiconductor substrate 102, provides additional electrical insulation between the one or more bumps 110, and/or protects the one or more bumps 110 from moisture and oxidation. In some embodiments, the underfill 118 is used in conjunction with the molding compound 112, as can be seen.

The molding compound 112 can be formed such that a backside surface of the one or more dies 108 is exposed to facilitate heat dissipation. In one embodiment, the molding compound 112 can be deposited using a mold that allows the molding compound 112 to be formed such that the backside surface of the one or more dies 108 is exposed. In other embodiments, the molding compound can be deposited to encapsulate the one or more dies and, subsequently, the molding compound can be recessed to expose the backside surface of the one or more dies 108.

FIG. 4 is a process flow diagram of a method 400 to fabricate a package assembly (e.g., the package assembly 200 of FIG. 2I) described herein. At 402, the method 400 includes providing a semiconductor substrate (e.g., the semiconductor substrate 102 of FIG. 2A). The semiconductor substrate generally comprises a first surface (e.g., the first surface A1 of FIG. 2A) and a second surface (e.g., the second surface A2 of FIG. 2A) that is disposed opposite to the first surface.

At 404, the method 400 further includes forming a dielectric film (e.g., the dielectric film 105 of FIG. 2A) on the semiconductor substrate. The dielectric film can be formed according to techniques described in connection with FIG. 2A.

At 406, the method 400 further includes forming a redistribution layer (e.g., the one or more redistribution layers 106 of FIG. 2B) on the semiconductor substrate. The redistribution layer can be formed according to techniques described in connection with FIG. 2B.

At 408, the method 400 further includes electrically coupling one or more dies (e.g., the one or more dies 108 of FIG. 2C) to the redistribution layer. The one or more dies can be coupled according to techniques described in connection with FIG. 2C.

At 410, the method 400 further includes forming a molding compound (e.g., the molding compound 112 of FIG. 2D) on the semiconductor substrate. The molding compound can be formed according to techniques described in connection with FIG. 2D.

At 412, the method 400 further includes recessing a surface (e.g., the second surface A2 of FIG. 2E) of the semiconductor substrate. The surface can be recessed according to techniques described in connection with FIG. 2E.

At 414, the method 400 further includes forming one or more channels (e.g., the one or more channels 104 of FIG. 2F and FIG. 2G) through the semiconductor substrate. The one or more channels can be formed according to techniques described in connection with FIGS. 2F and 2G.

At 416, the method 400 further includes forming one or more under bump metallization (UBM) structures (e.g., the one or more UBM structures 116 of FIG. 2H) in the one or more channels. The one or more UBM structures can be formed according to techniques described in connection with FIG. 2H.

At 418, the method 400 further includes forming one or more package interconnect structures (e.g., the one or more package interconnect structures 114 of FIG. 2I) in the one or more channels. The one or more package interconnect structures can be formed according to techniques described in connection with FIG. 2I.

Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.

Claims

1. A method comprising:

providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface;

forming a dielectric film on the first surface of the semiconductor substrate;

forming a redistribution layer on the dielectric film;

electrically coupling one or more dies to the redistribution layer;

forming a molding compound on the semiconductor substrate;

recessing the second surface of the semiconductor substrate;

forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and

forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies.

2. The method of claim 1, wherein the redistribution layer is formed by depositing an electrically conductive material on the dielectric film.

3. The method of claim 1, wherein the one or more dies are coupled to the redistribution layer in a flip-chip configuration.

4. The method of claim 1, wherein the molding compound is formed by depositing an electrically insulative material to substantially encapsulate the one or more dies.

5. The method of claim 1, wherein the semiconductor substrate is recessed by a grinding process or an etch process.

6. The method of claim 1, wherein the semiconductor substrate is recessed such that the semiconductor substrate has a thickness between about 50 microns and about 300 microns.

7. The method of claim 1, wherein the one or more channels are formed by:

selectively removing semiconductor material of the semiconductor substrate; and

selectively removing dielectric material of the dielectric film.

8. The method of claim 1, further comprising:

forming one or more under-ball metallization (UBM) structures in the one or more channels, the one or more UBM structures being formed on (i) the redistribution layer that is exposed by forming the one or more channels and (ii) the semiconductor substrate within the one or more channels, wherein the one or more package interconnect structures are coupled to the one or more UBM structures.

9. The method of claim 1, wherein the one or more package interconnect structures comprise solder balls that are formed by at least one of (i) screen printing, (ii) electrical plating, and (iii) solder ball placement.

10. The method of claim 1, further comprising:

forming an underfill layer between (i) the one or more dies and (ii) the semiconductor substrate.

11. The method of claim 1, wherein the one or more channels are formed subsequent to the molding compound being formed; and

the molding compound is used as a mechanical carrier to support the semiconductor substrate when the second surface of the semiconductor substrate is being recessed.

12. An apparatus comprising:

a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface;

a dielectric film formed on the first surface of the semiconductor substrate;

a redistribution layer formed on the dielectric film;

one or more dies electrically coupled to the redistribution layer;

a molding compound formed on the semiconductor substrate;

one or more channels formed through the second surface of the semiconductor substrate; and

one or more package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.

13. The apparatus of claim 12, wherein the one or more dies are coupled to the redistribution layer in a flip-chip configuration using one or more bumps.

14. The apparatus of claim 12, wherein the molding compound substantially encapsulates the one or more dies.

15. The apparatus of claim 12, wherein the second surface of the semiconductor substrate is recessed such that the semiconductor substrate has a thickness between about 50 microns and about 300 microns.

16. The apparatus of claim 12, further comprising:

one or more under-ball metallization (UBM) structures formed in the one or more channels, the one or more UBM structures being formed on (i) the redistribution layer and (ii) the semiconductor substrate within the one or more channels, wherein the one or more package interconnect structures are coupled to the one or more UBM structures.

17. The apparatus of claim 12, further comprising:

an underfill layer formed between (i) the one or more dies and (ii) the semiconductor substrate.

18. The apparatus of claim 12, wherein:

the one or more package interconnect structures comprise solder balls to route electrical signals of the one or more dies; and

the redistribution layer comprises an electrically conductive material to route the electrical signals of the one or more dies.

19. The apparatus of claim 12, wherein:

the semiconductor substrate comprises silicon;

the one or more dies comprise silicon; and

the one or more channels comprise one or more through-silicon vias.

20. The apparatus of claim 19, wherein:

the molding compound and the semiconductor substrate have a coefficient of thermal expansion (CTE) that is the same or substantially similar; and

the one or more through-silicon vias are tapered.